Trinh K Nguyen

US Patent:

6973471, Dec 6, 2005

Filed:

Feb 22, 2002

Appl. No.:

10/081431

Inventors:

Trinh Huy Nguyen - Pflugerville TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F007/52

US Classification:

708627, 708628, 708629

Abstract:

A multiplier () forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While recoding and partial product generation is occurring, a determination is made in parallel whether or not a sign extension adjustment term must be created. When needed, a value equal to (−B) (2), where N is equal to a bit width of the multiplicand (A), is formed in parallel with the recoding and partial product generation. The sign extension adjustment term is coupled to a plurality of carry save adders () that compress a plurality of partial products to a sum term and a carry term. A final add stage combines the sum term and carry term to provide a product with correct sign extension.

US Patent:

7698353, Apr 13, 2010

Filed:

Sep 14, 2005

Appl. No.:

11/226040

Inventors:

Dimitri Tan - Austin TX, US
Trinh H. Nguyen - Pflugerville TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 7/00

US Classification:

708205

Abstract:

A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.

US Patent:

7805581, Sep 28, 2010

Filed:

Feb 27, 2007

Appl. No.:

11/679590

Inventors:

Michael D. Snyder - Austin TX, US
David C. Holloway - Cedar Park TX, US
Trinh H. Nguyen - Round Rock TX, US
Sergio Schuler - Austin TX, US
Gary L. Whisenhunt - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/00

US Classification:

711154, 711170, 711E12084

Abstract:

A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

US Patent:

8117618, Feb 14, 2012

Filed:

Oct 12, 2007

Appl. No.:

11/871626

Inventors:

David C. Holloway - Cedar Park TX, US
Trinh H. Nguyen - Round Rock TX, US
Michael D. Snyder - Cedar Park TX, US
Gary L. Whisenhunt - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/46

US Classification:

718103, 718102

Abstract:

A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

US Patent:

20090245218, Oct 1, 2009

Filed:

Mar 31, 2008

Appl. No.:

12/079977

Inventors:

Trinh Nguyen - Grapevine TX, US

Assignee:

Alcatel Lucent - Paris

International Classification:

H04Q 7/28

US Classification:

370340

Abstract:

The present invention provides for giving preference to a specific media gateway in the selection of the next circuit so that in a multi-media-gateway soft-switch where a call may take any of many possible paths, an outgoing circuit on the same media-gateway as the incoming circuit is preferably selected, so if one is available, the need for using more bearer ports on media gateways to bridge the two sides is eliminated. Instead of interconnection, the same facilities can be provisioned to the bearer interface between the soft-switch and the rest of the network. This invention maximizes the bearer capacity of a distributed media gateway for external network access.

US Patent:

20120303936, Nov 29, 2012

Filed:

Mar 14, 2012

Appl. No.:

13/419531

Inventors:

Thang M. Tran - Austin TX, US
Trinh Huy Nguyen - Round Rock TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G06F 9/30
G06F 9/312
G06F 9/34

US Classification:

712208, 712E09028, 712E09033, 712E09038

Abstract:

In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues. One of the duplicate dependent instruction indicators is assigned to an execution queue for a dependent instruction. The dependent instruction is executed only when the one of the duplicate dependent instruction indicators is reset.

US Patent:

20130212358, Aug 15, 2013

Filed:

Feb 15, 2012

Appl. No.:

13/397452

Inventors:

Thang M. Tran - Austin TX, US
Trinh Huy Nguyen - Round Rock TX, US

International Classification:

G06F 9/30
G06F 9/312
G06F 9/38

US Classification:

712208, 712220, 712E09016, 712E09033, 712E09049

Abstract:

A data processing system comprises a processor unit that includes an instruction decode/issue unit including a re-order buffer having entries that include an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned, a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result, and a forward indicator to indicate that the status bit can be forwarded to an execution queue of an instruction pointed to that is waiting to receive the status bit.

US Patent:

57403996, Apr 14, 1998

Filed:

Aug 23, 1995

Appl. No.:

8/518348

Inventors:

Michael John Mayfield - Austin TX
Trinh Huy Nguyen - Pflugerville TX
Robert James Reese - Austin TX
Michael Thomas Vaden - Austin TX

Assignee:

International Business Machines Corporation

International Classification:

G06F 1208

US Classification:

395464

Abstract:

Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.