Timothy A Horel

US Patent:

6499135, Dec 24, 2002

Filed:

May 25, 2000

Appl. No.:

09/579109

Inventors:

Mu-Jing Li - Sunnyvale CA
Ward Vercruysse - San Jose CA
Pankaj Dixit - Mountain View CA
Timothy Horel - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 19, 716 21

Abstract:

For an integrated circuit having multiple metal layers, a computer-aided design (CAD) method for designing grounded fill in the integrated circuit includes: (a) finding the eligible fill areas for each metal layer; (b) storing the eligible fill area data for each metal layer in an overflow memory; (c) finding ground contact areas for each metal layer; (d) storing the ground contact area data for each metal layer in an overflow memory; (e) temporarily storing the eligible fill area data for a selected metal layer and the ground contact area data for the metal layers adjacent to the selected metal layer in active memory; (f) fitting a fill pattern to an eligible fill area in the selected metal layer, where the fill pattern is composed of at least one element; (g) checking the adjacent metal layers for a ground contact where the element of the fill pattern may be grounded; (h) locating a conductive via between the element of the fill pattern and a ground contact in an adjacent layer; and (i) repeating steps (e) through (h) for each metal layer.

US Patent:

6608335, Aug 19, 2003

Filed:

May 25, 2000

Appl. No.:

09/578919

Inventors:

Pankaj Dixit - Mountain View CA
Timothy Horel - Mountain View CA
Mu-Jing Li - Sunnyvale CA
Ward Vercruysse - San Jose CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H01L 2710

US Classification:

257211, 257207, 257758

Abstract:

An integrated circuit has a plurality of metal layers separated by a plurality of insulating layers. The integrated circuit comprises a pair of conductors on a first metal layer; at least one conductive fill element disposed between the conductors; and a via connecting the fill element to a ground contact on a metal layer adjacent to said first metal layer, where the via is formed of a conductive material.

US Patent:

7529992, May 5, 2009

Filed:

Mar 27, 2006

Appl. No.:

11/390973

Inventors:

Steven Teig - Menlo Park CA, US
Jason Redgrave - Mountain View CA, US
Timothy Horel - Mountain View CA, US

Assignee:

Tabula, Inc. - Santa Clara CA

International Classification:

G01R 31/28

US Classification:

714725

Abstract:

An integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data and error correction data, and error correction circuitry for receiving the configuration data, correcting a particular error in the received configuration data when the particular error exists in the configuration data, and outputting the configuration data without the particular error. The IC further includes a configurable circuit (e. g. , a configurable logic circuit or a configurable interconnect circuit) that receives the error-corrected configuration data from the error correction circuitry, and circuitry to write the corrected configuration data and error data back into the configuration memory.

US Patent:

8395454, Mar 12, 2013

Filed:

May 13, 2011

Appl. No.:

13/107079

Inventors:

Timothy Horel - Santa Clara CA, US

Assignee:

Oracle International Corporation - Redwood City CA

International Classification:

H03K 3/03

US Classification:

331 57, 331 55, 331 56

Abstract:

A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.