Thomas A Horvath

US Patent:

7359565, Apr 15, 2008

Filed:

May 3, 2004

Appl. No.:

10/836255

Inventors:

Krishna C. Ratakonda - Yorktown Heights NY, US
Cesar A. Gonzales - Katonah NY, US
Thomas A. Horvath - Stormville NY, US
Thomas McCarthy - Cortlandt Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06K 9/40
G06K 9/46

US Classification:

382260, 382232, 382254, 382275

Abstract:

A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H. 264/AVC. The filtering operation de-blocks or removes unwanted borders in the perceived video. During the filtering process, a series of filtering mask is generated based on temporal and spatial statistics of predictive encoded video information, which is then recursively applied to the video in order to gate filtered or unfiltered video to an output channel according to coefficients of the masks. The filtering mask effectively yields a decision or rule-based map that transforms the video on a pixel-by-pixel basis thereby avoiding complex and processor-intensive decision tree logic customarily required to process individual pixels of successive macroblocks that may have different filtering requirements.

US Patent:

8055091, Nov 8, 2011

Filed:

Jan 25, 2008

Appl. No.:

12/010449

Inventors:

Krishna C. Ratakonda - Yorktown Heights NY, US
Cesar A. Gonzales - Katonah NY, US
Thomas A. Horvath - Stormville NY, US
Thomas McCarthy - Cortlandt Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06K 9/40
G06K 9/46
G06K 9/00
G06K 9/38
H04B 1/66
H04N 7/12

US Classification:

382260, 382232, 382251, 382261, 382270, 375240, 3483841

Abstract:

A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H. 264/AVC. The filtering operation de-blocks or removes unwanted borders in the perceived video. During the filtering process, a series of filtering mask is generated based on temporal and spatial statistics of predictive encoded video information, which is then recursively applied to the video in order to gate filtered or unfiltered video to an output channel according to coefficients of the masks. The filtering mask effectively yields a decision or rule-based map that transforms the video on a pixel-by-pixel basis thereby avoiding complex and processor-intensive decision tree logic customarily required to process individual pixels of successive macroblocks that may have different filtering requirements.

US Patent:

8130228, Mar 6, 2012

Filed:

Jun 13, 2008

Appl. No.:

12/139224

Inventors:

Thomas A. Horvath - Stormville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/80
G06F 13/14
G06F 11/00
G09G 5/36
G11C 29/00

US Classification:

345505, 345520, 345557, 714804, 714805

Abstract:

A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a plurality of input ports for receiving the LDPC codes from some of the processing units, and a plurality of output ports for sending the LDPC codes to others of the processing units. An off-chip, external memory stores the LDPC codes and transmits the LDPC codes to and receives the LDPC codes from at least some of the processing units. A sequence processor controls the transmission of the LDPC codes between the processor units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence.

US Patent:

8514237, Aug 20, 2013

Filed:

May 22, 2007

Appl. No.:

11/752017

Inventors:

Thomas A. Horvath - Stormville NY, US
Brent Paulovicks - Danbury CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 5/36

US Classification:

345557

Abstract:

A computer readable medium is provided embodying instructions executable by a processor to perform a method for caching video data in a two-dimensional cache. The method includes storing the video data in the two-dimensional cache, addressing stored video data in the two-dimensional cache using a first tag for referencing video data of a first dimension, addressing the stored video data in the cache in terms of a second tag for referencing video data of a second dimension, and retrieving and outputting a portion of the stored video data from the two-dimensional cache according to one of the first tag and the second tag.

US Patent:

20070250681, Oct 25, 2007

Filed:

Apr 10, 2006

Appl. No.:

11/401130

Inventors:

Thomas Horvath - Stormville NY, US
Thomas McCarthy - Cortland Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/00

US Classification:

712004000

Abstract:

The present invention provides methods, systems and apparatus to control instruction sequencing for a vector processor in a parallel processing environment. It enhances standard Vector Processing architectures by using two independent processing units working in conjunction to produce a highly efficient data processing ensemble. In an example embodiment, the two processors include a Scalar Processor and a separate Vector Processor. The Scalar Processor has its own Instruction Store, General Purpose Registers and Arithmetic Logic Unit. It can execute a standard instruction set including branch and jump instructions. It's function is to control the processing sequence of the Vector Processor. The Vector Processor has an independent Instruction Store, a dedicated Register along with dedicate functional elements to perform vector operations. The Vector Processor does not execute any sequencing instructions such as branch or jump but executes a serial instruction sequence starting and ending at locations determined by the Scalar Processor.

US Patent:

52895777, Feb 22, 1994

Filed:

Jun 4, 1992

Appl. No.:

7/894121

Inventors:

Cesar A. Gonzales - Somers NY
Thomas A. Horvath - Stormville NY
Norman H. Kreitzer - Yorktown Heights NY
Andy G. Lean - Merrick NY
Thomas McCarthy - Peekskill NY

Assignee:

International Business Machines Incorporated - Armonk NY

International Classification:

G06F 314

US Classification:

395163

Abstract:

A sequential process-pipeline (12) has a first processing stage (30) coupled to a CODEC (24) through a plurality of buffers, including an image data input buffer (28), an image data output buffer (26), and an address buffer (34). The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory (22). Each block of addresses in the image memory stores a block of decompressed image data. A local controller (18) is responsive to the writing of an address into the address buffer to initiate the operation of the CODEC to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.

US Patent:

57579679, May 26, 1998

Filed:

Oct 19, 1995

Appl. No.:

8/545046

Inventors:

Cesar Augusto Gonzales - Katonah NY
Thomas Akos Horvath - Stormville NY
Elliot Neil Linzer - Bronx NY
Prasoon Tiwari - Yorktown Heights NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

G06K 900

US Classification:

382233

Abstract:

A video decoder/format/frame rate converter with common memory is provided. This device decodes a compressed, interlaced video stream and converts the decoded output to a non-interlaced format and/or a format with a different frame rate.

US Patent:

52764370, Jan 4, 1994

Filed:

Apr 22, 1992

Appl. No.:

7/872739

Inventors:

Thomas A. Horvath - Stormville NY
Inching Chen - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 106

US Classification:

345119

Abstract:

An apparatus and method for displaying non-obscured pixels in a multiple-media motion video environment (dynamic image management) possessing overlaid windows. In an encoding process, only boundary values and identification values corresponding to each window on a screen are saved in memory of a hardware device. In a decoding process, the hardware device utilizes these initial boundary values saved in memory in such a way that when incoming video data enters the hardware device, the hardware device need only compare the incoming video data's identification with the identification saved in memory. The hardware device includes: compare logic devices, counters, minimal memory devices, a control logic block, and a driver.