Thomas L Dmukauskas

US Patent:

20050251642, Nov 10, 2005

Filed:

May 3, 2004

Appl. No.:

10/838078

Inventors:

Jose Niell - Franklin MA, US
Gilbert Wolrich - Framingham MA, US
Thomas Dmukauskas - Cambridge MA, US
Mark Rosenbluth - Uxbridge MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711201000

Abstract:

Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.

US Patent:

20180164864, Jun 14, 2018

Filed:

Dec 14, 2016

Appl. No.:

15/379283

Inventors:

- Santa Clara CA, US
Sean M. Gulley - Boston MA, US
Thomas L. Dmukauskas - Somerville MA, US
Aaron Gorius - Upton MA, US
Vinodh Gopal - Westborough MA, US

International Classification:

G06F 1/28
G01R 31/28
G06F 1/32

Abstract:

Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.