Thomas O Curlee

Author:

Thomas N. Curlee

ISBN #:

0830627014

US Patent:

58190619, Oct 6, 1998

Filed:

Jul 25, 1994

Appl. No.:

8/279588

Inventors:

Steven Gardner Glassen - Wallkill NY
Robert Stanley Capowski - Verbank NY
Neal Taylor Christensen - Wappingers Falls NY
Thomas Oscar Curlee - Poughkeepsie NY
Ronald Franklin Hill - Wappingers Falls NY
Moon Ju Kim - Wappingers Falls NY
Matthew Anthony Krygowski - Hopewell Junction NY
Allen Herman Preston - Poughkeepsie NY
David Emmett Stucki - Poughkeepsie NY
Frederick J. Cox - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

395406

Abstract:

In a partitioned process environment, storage is reassigned by a shuffle of guest absolute address spaces which may be reassigned among partitions without restriction as to the position of the space to be reassigned relative to the position of the partition to which it is to be assigned. The reassignment is accomplished by adjusting the origin addresses by an adjustment value corresponding to the size of the address space of an additional memory area to be added to a selected partition. Furthermore, the size of the address space of the selected partition is increased by the same adjustment value. The system employs duplicated origin and limit arrays which are used to convert from a partition (guest) absolute address to a system (host) absolute address and uses duplicated configuration arrays by which the system absolute addresses are converted to physical memory addresses. Revised origin and limit information and configuration information is stored in an origin and limit array in the stand by state and in a configuration array in the stand by state. Autonomously operating circuitry is responsive to control signals to temporarily suspend memory commands from the input-output system, to reconfigure the origin and limit arrays and the configuration arrays to enable the system to use the revised information and, thereafter, to resume the processing of memory commands from the input-output system.

US Patent:

47791888, Oct 18, 1988

Filed:

Oct 19, 1987

Appl. No.:

7/110620

Inventors:

Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Highland NY
Peter H. Tallman - Poughkeepsie NY
Thomas O. Curlee - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 944
G06F 932

US Classification:

364200

Abstract:

The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

US Patent:

44569548, Jun 26, 1984

Filed:

Jun 15, 1981

Appl. No.:

6/273532

Inventors:

Robert J. Bullions - Poughkeepsie NY
Thomas O. Curlee - Poughkeepsie NY
Peter H. Gum - Poughkeepsie NY
Bruce L. McGilvray - Pleasant Valley NY
Ethel L. Richardson - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 944
G06F 932

US Classification:

364200

Abstract:

Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.