Terri A Danowski

US Patent:

55133380, Apr 30, 1996

Filed:

Mar 12, 1993

Appl. No.:

8/030801

Inventors:

James W. Alexander - Hillsboro OR
Terri A. Danowski - Aloha OR
Stephen J. Peters - Aloha OR
Ronald J. Whitsel - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100
G06F 1300

US Classification:

395500

Abstract:

An in-circuit emulator trace bus clocking mechanism. A synchronization clock associated with the trace bus is provided. Arrival of a first event on a microprocessor bus to be traced is signified by a transition of a control line. A start of cycle event is detected. A start of cycle signal is generated with respect to the start of cycle event. A two stage pipeline having stage 1 storage elements and stage 2 storage elements are connected to receive data from the microprocessor bus. The start of cycle signal is used to sample data from the microprocessor bus into the stage 1 storage elements. An end of cycle event is detected. An end of cycle signal is generated with reference to the end of cycle event. The end of cycle signal is used to sample data from the stage 1 storage elements into the stage 2 storage elements. The end of cycle signal is also used to sample data appearing on the microprocessor bus at the end of the cycle into the stage 2 storage elements.