Takeshi Yamazaki

US Patent:

6779049, Aug 17, 2004

Filed:

Dec 14, 2000

Appl. No.:

09/736585

Inventors:

Erik R. Altman - Danbury CT
Peter G. Capek - Ossining NY
Michael Gschwind - Chappaqua NY
Harm Peter Hofstee - Austin TX
James Allan Kahle - Austin TX
Ravi Nair - Briarcliff Manor NY
Sumedh Wasudeo Sathaye - Lagrangeville NY
John-David Wellman - Hopewell Junction NY
Masakazu Suzuoki - Austin TX
Takeshi Yamazaki - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 22, 710 26, 711147, 711153, 711173, 711202, 711203, 711205, 711206, 711207, 711208

Abstract:

A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

US Patent:

6919896, Jul 19, 2005

Filed:

Mar 11, 2002

Appl. No.:

10/095213

Inventors:

Nobuo Sasaki - Tokyo, JP
Takeshi Yamazaki - Austin TX, US

Assignee:

Sony Computer Entertainment Inc.

International Classification:

G06F015/80

US Classification:

345505, 345506, 345531, 345536, 345581, 709248, 709400

Abstract:

A method and system for optimizing the processing of graphics is disclosed. The system may comprise at least one geometry processor and at least one graphics processor. A communication channel permits communication between the geometry and graphics processors. A control processor may communicate with the geometry and graphics processor through the communications channel. A method of processing graphics data in a computer system is provided to determine whether the geometry and graphics processors are being efficiently utilized. If necessary, one or more of the geometry and graphics processors are selectively assigned or unassigned to improve the efficiency of the graphics processing circuitry in performing the graphics task.

US Patent:

7099975, Aug 29, 2006

Filed:

Dec 9, 2003

Appl. No.:

10/730952

Inventors:

Jeffrey Douglas Brown - Rochester MN, US
Scott Douglas Clark - Rochester MN, US
Charles Ray Johns - Austin TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

710240, 710243, 710244

Abstract:

An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

US Patent:

7107363, Sep 12, 2006

Filed:

Jun 19, 2003

Appl. No.:

10/464882

Inventors:

Jeffrey Douglas Brown - Rochester MN, US
Michael Norman Day - Round Rock TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00

US Classification:

710 18, 712 10

Abstract:

The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.

US Patent:

7114035, Sep 26, 2006

Filed:

Sep 4, 2003

Appl. No.:

10/655365

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133

Abstract:

The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

US Patent:

7120748, Oct 10, 2006

Filed:

Sep 4, 2003

Appl. No.:

10/655367

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Roy Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133

Abstract:

The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia.

US Patent:

7200688, Apr 3, 2007

Filed:

May 29, 2003

Appl. No.:

10/448237

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
Thuong Quang Truong - Austin TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28

US Classification:

710 22, 710 5, 710 20, 710 24, 710 62, 710312

Abstract:

The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.

US Patent:

7203811, Apr 10, 2007

Filed:

Jul 31, 2003

Appl. No.:

10/631542

Inventors:

Matthew Edward King - Pflugerville TX, US
David Mui - Round Rock TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G00F 13/28

US Classification:

711169, 710 22, 710 24, 710308

Abstract:

A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.