Takao Akaogi

US Patent:

6347052, Feb 12, 2002

Filed:

Oct 17, 2000

Appl. No.:

09/690554

Inventors:

Takao Akaogi - Cupertino CA
Ali K. Al-Shamma - San Jose CA
Lee Cleveland - Santa Clara CA
Yong Kim - Santa Clara CA
Kendra Nguyen - San Jose CA
Boon Tang Teh - Penang, MY

Assignee:

Advanced Micro Devices Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1606

US Classification:

36518523, 36518909, 36523006

Abstract:

A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit.

US Patent:

6351420, Feb 26, 2002

Filed:

Jun 16, 2000

Appl. No.:

09/595519

Inventors:

Takao Akaogi - Cupertino CA
Ali K. Al-Shamma - San Jose CA
Lee Edward Cleveland - Santa Clara CA
Yong Kim - Santa Clara CA
Boon Tang Teh - Santa Clara CA
Kendra Nguyen - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 700

US Classification:

36518909, 36518906, 36518911, 365226, 327538

Abstract:

A voltage boost circuit ( ) for a flash memory ( ) includes a boosting circuit ( ), which is capable of boosting a portion of a power supply voltage (V ) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array ( ) of the memory. The voltage boost circuit further includes a balancing or clamping circuit ( ) for providing a nonzero adjustment voltage (V ) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

US Patent:

6353566, Mar 5, 2002

Filed:

Sep 18, 2000

Appl. No.:

09/663552

Inventors:

Takao Akaogi - Cupertino CA
Kazuhiro Kurihara - Sunnyvale CA
Thomas T. Shieh - San Jose CA

Assignee:

Advanced Micro Devices - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 700

US Classification:

365203, 36518525, 365202

Abstract:

A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization pulse which is used to equalize the output stage of the sense amplifier to the input stage.

US Patent:

6359808, Mar 19, 2002

Filed:

Oct 19, 1999

Appl. No.:

09/421985

Inventors:

Tien-Min Chen - San Jose CA
Kazuhiro Kurihara - Sunnyvale CA
Takao Akaogi - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1606

US Classification:

36518521, 36518533

Abstract:

A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special âkickerâ circuitry raises the sense pre-amplifiers input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.

US Patent:

6400633, Jun 4, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/675372

Inventors:

Ali Al-Shamma - San Jose CA
Takao Akaogi - Cupertino CA
Lee Cleveland - Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 700

US Classification:

365227, 36518901, 365228

Abstract:

A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

US Patent:

6400638, Jun 4, 2002

Filed:

Oct 5, 2000

Appl. No.:

09/680344

Inventors:

Shigekazu Yamada - Cupertino CA
Takao Akaogi - Cupertino CA
Colin S. Bill - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 800

US Classification:

36523006, 365226, 365211

Abstract:

The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.

US Patent:

6463003, Oct 8, 2002

Filed:

Dec 4, 2000

Appl. No.:

09/729388

Inventors:

Ali K. Al-Shamma - San Jose CA
Takao Akaogi - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 800

US Classification:

365227, 365226

Abstract:

Reading data from a core memory consumes more power when the data sets being driven change state, especially when bursting out the data at high speed. Power saving for a burst mode implementation improves the power consumed by inverting the data sets whenever a majority of the data changes states from set to set and including a separate output indicating whether the data being driven is inverted. Present data is selected from the core memory and clocked into the power saving arrangement. The present data is compared with previously selected data to determine whether the majority of data presently selected has changed from the previously selected data. In addition, the present selected data is also delayed and then subjected to a logical XOR function with the majority determination above. Finally, the data subjected to the logical XOR function and the majority determination are driven separately to external elements requesting the present data. Thus, power is saved as the state of the majority of the data being driven from one data set to the next remains unchanged.

US Patent:

6487060, Nov 26, 2002

Filed:

Jul 27, 2001

Appl. No.:

09/916382

Inventors:

Takao Akaogi - Cupertino CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H02H 322

US Classification:

361111

Abstract:

A protection system that protects a booster circuit used to boost operating signals in a memory device. The system includes a protection circuit for protecting an output transistor of the booster circuit. The protection circuit includes a transfer gate coupled to the output transistor and coupled to receive a first boost signal and a second boost signal. The transfer gate opens and closes in response to the second boost signal. When the transfer gate is closed, the first boost signal is uncoupled from the output transistor, and when the transfer gate is opened, the first boost signal is coupled to the output transistor. The circuit also includes a protection transistor coupled to the second boost signal, a supply voltage and the output transistor, where the protection transistor couples the supply voltage to the output transistor when the transfer gate is closed.