Suresh Te Sivasubramaniam

US Patent:

7281233, Oct 9, 2007

Filed:

May 27, 2005

Appl. No.:

11/140020

Inventors:

Suresh Sivasubramaniam - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 15, 716 18

Abstract:

Method and apparatus for implementing a circuit design for at least one integrated circuit on a circuit board is described. In one example, a logical description of the circuit design is obtained. For example, a functional description of the circuit design may be synthesized to produce the logical description. Logical pins in the logical description are assigned to input/output (I/O) elements of the at least one integrated circuit, and the logical description is placed and routed for the at least one integrated circuit, based on external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit.

US Patent:

8520402, Aug 27, 2013

Filed:

Oct 25, 2005

Appl. No.:

11/258681

Inventors:

Suresh Sivasubramaniam - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H05K 1/11
H05K 1/14

US Classification:

361794, 361790, 361795, 361803, 174259, 174260

Abstract:

Decoupling capacitor circuit assembly is described. In one example, a circuit assembly includes a passive substrate, a plurality of terminals, and at least one capacitor. The passive substrate includes a top surface and a bottom surface. The plurality of terminals is formed on the top surface and is configured for electrical communication with a respective plurality of lands on a printed circuit board (PCB). The at least one capacitor is mounted to the bottom surface of the passive substrate and is configured to provide decoupling capacitance for an integrated circuit (IC) on the PCB. Each capacitor is coupled to a pair of the plurality of terminals. In another example, a circuit assembly includes a PCB, and IC mounted to the PCB, a passive substrate mounted to the PCB, and at least one capacitor mounted to the passive substrate for providing decoupling capacitance for the IC.

US Patent:

6728647, Apr 27, 2004

Filed:

Feb 21, 2001

Appl. No.:

09/792134

Inventors:

Suresh Sivasubramaniam - San Jose CA
Siuki Chan - Cupertino CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 2700

US Classification:

702 65, 324681

Abstract:

A method of estimating a capacitance of each resource in a programmable logic device (PLD) is described. The current drawn by a reference circuit implemented in the PLD is measured at a given frequency and operating voltage. The capacitance of the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The current drawn by a resource load coupled to the reference circuit is measured at the given frequency and operating voltage. The capacitance of the resource load coupled to the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The capacitance of the resource load may be calculated by subtracting the capacitance of the reference circuit from the capacitance of the resource load coupled to the reference circuit.