NVIDIA - Santa Clara, CA since Jun 2006
Sr. Hardware Design Engineer (Lead - Tegra Clocks)
Intel Corporation - Santa Clara, CA Aug 2005 - Jun 2006
Component Design Engineer
Imation Corporation May 2004 - Jul 2004
Intern
Education:
University of Minnesota 2003 - 2005
MS, Computer Engineering
University of Mumbai 2000 - 2003
BE, Electronics Engineering
Larsen and Toubro Institute of Technology 1996 - 2000
Diploma, Electronics Engineering
Skills:
Soc Computer Architecture Timing Verilog Asic Static Timing Analysis Primetime Ic Rtl Design Vlsi Systemverilog Logic Design Timing Closure Vhdl Debugging System on A Chip Integrated Circuit Design Dft Processors Low Power Design Eda Circuit Design Microprocessors