Suraj Te Dalvi
age ~44
from Cupertino, CA
- Also known as:
-
- Suraj T Dalvi
- Suraj Calvi
- Phone and address:
- 19731 La Mar Dr, Cupertino, CA 95014
Suraj Dalvi Phones & Addresses
- 19731 La Mar Dr, Cupertino, CA 95014
- 815 E Fremont Ave APT 15, Sunnyvale, CA 94087
- Minneapolis, MN
- Santa Clara, CA
- 815 E Fremont Ave APT 55, Sunnyvale, CA 94087
Work
-
Company:NvidiaJun 2006
-
Address:Santa Clara, CA
-
Position:Sr. hardware design engineer (lead - tegra clocks)
Education
-
Degree:MS
-
School / High School:University of Minnesota2003 to 2005
-
Specialities:Computer Engineering
Skills
Soc • Computer Architecture • Timing • Verilog • Asic • Static Timing Analysis • Primetime • Ic • Rtl Design • Vlsi • Systemverilog • Logic Design • Timing Closure • Vhdl • Debugging • System on A Chip • Integrated Circuit Design • Dft • Processors • Low Power Design • Eda • Circuit Design • Microprocessors
Languages
English • Marathi • Hindi
Interests
Music • Movies
Industries
Computer Hardware
Resumes
Senior Manager, Hardware Engineering
view sourceLocation:
19731 La Mar Dr, Cupertino, CA 95014
Industry:
Computer Hardware
Work:
NVIDIA - Santa Clara, CA since Jun 2006
Sr. Hardware Design Engineer (Lead - Tegra Clocks)
Intel Corporation - Santa Clara, CA Aug 2005 - Jun 2006
Component Design Engineer
Imation Corporation May 2004 - Jul 2004
Intern
Sr. Hardware Design Engineer (Lead - Tegra Clocks)
Intel Corporation - Santa Clara, CA Aug 2005 - Jun 2006
Component Design Engineer
Imation Corporation May 2004 - Jul 2004
Intern
Education:
University of Minnesota 2003 - 2005
MS, Computer Engineering University of Mumbai 2000 - 2003
BE, Electronics Engineering Larsen and Toubro Institute of Technology 1996 - 2000
Diploma, Electronics Engineering
MS, Computer Engineering University of Mumbai 2000 - 2003
BE, Electronics Engineering Larsen and Toubro Institute of Technology 1996 - 2000
Diploma, Electronics Engineering
Skills:
Soc
Computer Architecture
Timing
Verilog
Asic
Static Timing Analysis
Primetime
Ic
Rtl Design
Vlsi
Systemverilog
Logic Design
Timing Closure
Vhdl
Debugging
System on A Chip
Integrated Circuit Design
Dft
Processors
Low Power Design
Eda
Circuit Design
Microprocessors
Computer Architecture
Timing
Verilog
Asic
Static Timing Analysis
Primetime
Ic
Rtl Design
Vlsi
Systemverilog
Logic Design
Timing Closure
Vhdl
Debugging
System on A Chip
Integrated Circuit Design
Dft
Processors
Low Power Design
Eda
Circuit Design
Microprocessors
Interests:
Music
Movies
Movies
Languages:
English
Marathi
Hindi
Marathi
Hindi
Googleplus
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Suraj Dalvi
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Suraj Dalvi
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Suraj Dalvi
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Suraj Dalvi
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Suraj Dalvi
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Suraj Dalvi
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Suraj Dalvi
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Suraj Dalvi
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