Sunil R Patel

US Patent:

6335491, Jan 1, 2002

Filed:

Feb 8, 2000

Appl. No.:

09/499801

Inventors:

Maniam Alagaratnam - Cupertino CA
Kishor V. Desai - Fremont CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 116

US Classification:

174260, 174261, 174262, 361760, 257686, 257738, 257778

Abstract:

The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

US Patent:

6466038, Oct 15, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/727427

Inventors:

Senol Pekin - San Jose CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3126

US Classification:

324719, 324537, 324717, 3241581

Abstract:

A method for measuring electromigration includes the steps of measuring a corresponding voltage increase across an interconnect as a function of time for a plurality of nonzero heating rates and calculating an interconnect integrity from the voltage increase.

US Patent:

6618938, Sep 16, 2003

Filed:

Oct 9, 2001

Appl. No.:

09/974157

Inventors:

Maniam Alagaratnam - Cupertino CA
Kishor V. Desai - Fremont CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 334

US Classification:

29840, 29739, 29825, 29832, 22818021, 22818022

Abstract:

The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

US Patent:

6306751, Oct 23, 2001

Filed:

Sep 27, 1999

Appl. No.:

9/406308

Inventors:

Sunil A. Patel - Los Altos CA
Chok J. Chia - Cupertino CA
Kishor V. Desai - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2144

US Classification:

438614

Abstract:

Provided is an apparatus and method for modifying the manufacture of chip carrier bond pads to increase the quality and reliability of semiconductor packages and ball joints in particular. This is accomplished by minimizing the corrosion of the barrier metal layer on the functional bond pads during gold deposition with the use of sacrificial pads electrically connected with the functional bond pads. According to one embodiment of the invention, a semiconductor package has copper conductive pads on a substrate that are exposed through a dielectric. Both functional and sacrificial (nonfunctional) copper conductive pads are provided. A barrier metal layer composed of nickel is electrolessly plated onto these conductive pads, and a bond metal layer of gold is deposited onto the nickel using electroless, generally immersion, gold plating. The surface area of the nickel on the sacrificial pads is less than that on the functional pads, and the nickel on the sacrificial pads corrodes first during electroless gold deposition. Without nickel corrosion on the functional bond pad, gold can more uniformly be deposited on the surface of the nickel layer.

US Patent:

60202211, Feb 1, 2000

Filed:

Dec 12, 1996

Appl. No.:

8/764039

Inventors:

Ramaswamy Ranganathan - Cupertino CA
Sunil A. Patel - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2152
H01L 2158
H01L 2160

US Classification:

438125

Abstract:

The subject method comprises providing a semiconductor package and a semiconductor package substrate having respective first and second major sides. A stiffener member, which is attachable to the semiconductor package substrate, is employed for purposes of minimizing package warpage. The stiffener member is attached to the semiconductor package substrate to provide the requisite support for the semiconductor package substrate during the assembly process and thereby counteract the sources of the package warpage problem. A protective outer layer can be optionally added to the subject system.