Sunil Bhardwaj

US Patent:

20110122687, May 26, 2011

Filed:

Nov 24, 2009

Appl. No.:

12/624856

Inventors:

Jungtae Kwon - San Jose CA, US
David Kim - Cupertino CA, US
Sunil Bhardwaj - San Jose CA, US

Assignee:

Innovative Silicon ISi SA - Lausanne

International Classification:

G11C 7/00
G11C 7/06
G11C 16/34

US Classification:

36518502, 365200

Abstract:

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

US Patent:

20120218847, Aug 30, 2012

Filed:

May 7, 2012

Appl. No.:

13/465982

Inventors:

Jungtae KWON - San Jose CA, US
David KIM - Cupertino CA, US
Sunil BHARDWAJ - San Jose CA, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 7/06

US Classification:

365207

Abstract:

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

US Patent:

20140056090, Feb 27, 2014

Filed:

Nov 1, 2013

Appl. No.:

14/069730

Inventors:

David KIM - Cupertino CA, US
Sunil BHARDWAJ - San Jose CA, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 7/02
G11C 7/06
G11C 7/08

US Classification:

365207

Abstract:

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

US Patent:

20140307512, Oct 16, 2014

Filed:

Jun 24, 2014

Appl. No.:

14/313654

Inventors:

- Boise ID, US
David KIM - Cupertino CA, US
Sunil BHARDWAJ - San Jose CA, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 7/02
G11C 7/08

US Classification:

36518902, 365207

Abstract:

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.