Sunhyuk H Kimn

US Patent:

59960655, Nov 30, 1999

Filed:

Mar 31, 1997

Appl. No.:

8/831473

Inventors:

Sivakumar Makineni - Sunnyvale CA
Brian L. Hughes - Fremont CA
Sunhyuk Kimn - Campbell CA
Michael Chow - Cupertino CA
Suri Babu Medapati - Santa Clara CA
Albert Lo - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 938

US Classification:

712218

Abstract:

A microprocessor having a pipelined floating point unit operable to bypass pre-rounded results at clock cycle i and provide the pre-rounded results as an operand for a second instruction at clock cycle i+2. In one embodiment, the pipelined execution unit includes at least a first execution step at clock cycle i, and a second execution step at a clock cycle i+1 and clock cycle i+2. The unit includes a bypass leading from the first execution step at clock cycle i, however, there is no bypass leading from the second execution step at clock cycle i+1. The bypass carries the pre-rounded results from the end of the first execution step to the front end of the pipeline via a latched data path which delays the pre-rounded result one clock cycle.