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Sudhi R Proch

age ~49

from McKinney, TX

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Also known as:
  • Sudhi Ranjan Proch
  • Sudhi H Proch
  • Sudhi Proh
  • Proch Sudhi
Connected to:

Sudhi Proch Phones & Addresses

  • McKinney, TX
  • Richardson, TX
  • Gainesville, FL
  • 6263 Mcneil Rd, Austin, TX 78729 • 512 257-9861
  • 12342 Hunters Chase Dr, Austin, TX 78729 • 512 257-9861
  • 11800 Grant Rd, Cypress, TX 77429 • 281 251-6890
  • Lehigh Valley, PA

Work

  • Company:
    Texas instruments
    Jun 1, 2014
  • Position:
    Analog and mixed signal design verification lead

Education

  • Degree:
    Masters
  • School / High School:
    University of Florida
    2012 to 2014
  • Specialities:
    Computer Engineering

Skills

Verilog • Functional Verification • Vhdl • Logic Design • Logic Synthesis • Embedded Systems • Systemverilog • Microcontrollers • Timing Closure • Matlab • Digital Circuit Design • Fpga Prototyping • Pci Standards • Spice • Xilinx Ise • Verilog Ams • Mixed Signal Verification • Ddr • Ddr3 • Ddr2 • Conformal Lec • Codewarrior • Perl Automation • Ansi C • Mixed Signal Ic Verification • Cadence Virtuoso

Industries

Semiconductors

Resumes

Sudhi Proch Photo 1

Analog And Mixed Signal Design Verification Lead

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Analog and Mixed Signal Design Verification Lead
University of Florida Aug 2012 - May 2014
Graduate Student and Research Assistant
Freescale Semiconductor Mar 2010 - Aug 2012
Ddr Phy Designer
Freescale Semiconductor Jan 2008 - Aug 2012
Soc Design Lead
Freescale Semiconductor Nov 2005 - Jan 2008
Soc Verification Lead
Education:
University of Florida 2012 - 2014
Masters, Computer Engineering Motilal Nehru National Institute of Technology 1994 - 1998
Bachelor of Engineering, Bachelors, Electronics
Skills:
Verilog
Functional Verification
Vhdl
Logic Design
Logic Synthesis
Embedded Systems
Systemverilog
Microcontrollers
Timing Closure
Matlab
Digital Circuit Design
Fpga Prototyping
Pci Standards
Spice
Xilinx Ise
Verilog Ams
Mixed Signal Verification
Ddr
Ddr3
Ddr2
Conformal Lec
Codewarrior
Perl Automation
Ansi C
Mixed Signal Ic Verification
Cadence Virtuoso

Us Patents

  • Method For Generating Reusable Behavioral Code

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  • US Patent:
    20050028035, Feb 3, 2005
  • Filed:
    Jul 31, 2003
  • Appl. No.:
    10/631536
  • Inventors:
    Sundeep Chadha - Austin TX, US
    Maureen Davis - Austin TX, US
    Sudhi Proch - Austin TX, US
    Tony Sawan - Round Rock TX, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F011/00
  • US Classification:
    714030000
  • Abstract:
    A waveform viewer implemented method of generating and manipulating user specified language simulation code such that an integrated circuit digital design can be modified. The visual capabilities of the waveform viewer allow a plurality of inputs for processing. The previous test's user specified language lines and the original signal waveforms are viewable on the same screen as the new code lines and waveforms. The waveform viewer also displays the contents of the portable reusable code portable reusable coded storage device. Each line of code and every signal can be manipulated by the user within the waveform viewer. The modified code output is applied to the test sequence through the waveform viewer, and the integrated circuit is retested with the new code. After modifications to the integrated circuit are complete, the proved device's stored user specified language can be transported to and inserted in other device architectures.

  • Method, System And Program Product For Facilitating Debugging Of Simulation Results Obtained For An Optimized Simulation Model Of A Device Design Having Hierarchically-Connected Components

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  • US Patent:
    20070168741, Jul 19, 2007
  • Filed:
    Nov 17, 2005
  • Appl. No.:
    11/282091
  • Inventors:
    Sundeep Chadha - Austin TX, US
    Sudhi Proch - Austin TX, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F 11/00
  • US Classification:
    714038000
  • Abstract:
    A computer-implemented processing tool is provided for facilitating debugging of simulation results obtained for an optimized simulation model of a device having hierarchically-connected components. The tool includes: receiving a component port name of the device to be searched; automatically checking a hardware descriptive language description of the device for a next higher level component of the device that instantiates the component having the component port name to be searched; locating a signal name in the next higher level component that is connected to the port identified by the component port name; and outputting the signal name as a signal that drives the named component port when the signal is other than a port signal of the next higher level component. Otherwise, repeating the automatically checking and the locating when the signal name in the next higher level component is a port signal of a further higher level component.

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Sudhi Proch Cypress TX

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Sudhi Proch

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