Subramanian S Meiyappan

US Patent:

6519670, Feb 11, 2003

Filed:

Feb 4, 2000

Appl. No.:

09/498399

Inventors:

Subramanian S. Meiyappan - Tempe AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1300

US Classification:

710305, 710110, 710240, 712 32

Abstract:

In an example embodiment, a data transaction access system for an embedded microprocessor coupled to a PCMCIA bus device comprises a local bus adapted to convey digital signals. Coupled to the local bus is a bus master. A host bus adapter couples to the local bus for enabling communication between the bus master and a PCMCIA device coupled to the host bus adapter via a PCMCIA bus. A wait register is coupled to the host bus adapter. The wait register is adapted to receive a delay input describing a latency period of the PCMCIA device, wherein the host bus adapter is configured to insert wait states into a data transaction from the bus master to the PCMCIA device when the delay input is less than a predetermined amount and wherein the host bus adapter is configured to retry the bus master when the delay input is greater than the predetermined amount.

US Patent:

6523075, Feb 18, 2003

Filed:

Sep 2, 1999

Appl. No.:

09/389871

Inventors:

Ken Jaramillo - Phoenix AZ
Brian Logsdon - Glendale AZ
Franklyn H. Story - Chandler AZ
Subramanian Meiyappan - Tempe AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1336

US Classification:

710113

Abstract:

A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. A bus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block. Alternatively, a centralized test device controller is used to disable the output of the second functional block, as opposed to using the grant signals of the bus arbiter.

US Patent:

6560663, May 6, 2003

Filed:

Sep 2, 1999

Appl. No.:

09/389873

Inventors:

Brian Logsdon - Glendale AZ
Franklyn H. Story - Chandler AZ
Ken Jaramillo - Phoenix AZ
Subramanian Meiyappan - Tempe AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1336

US Classification:

710113

Abstract:

A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block.

US Patent:

6578098, Jun 10, 2003

Filed:

Nov 4, 1999

Appl. No.:

09/435133

Inventors:

Subramanian Meiyappan - Tempe AZ
James J. Jirgal - Chandler AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1300

US Classification:

710110, 710104, 710105, 710106

Abstract:

The present invention is drawn to a computer implemented method and system for synchronously driving slave responses onto an ASB (advanced system bus) bus. On the one hand, in response to a read transfer from a ASB master, an ASB slave predicts the read transfer to be intended for a device attached to the ASB slave if the device is ready to return read data. On the other hand, in response to a write transfer from the ASB master, the ASB slave predicts the write transfer to be intended for the device attached to the ASB slave. In both scenarios, a device select signal (Dsel) is utilized to validate these two predictions. That is, the read slave response driven by the ASB slave does not enter the ASB bus when the device select signal does not select the ASB slave. Also, the write slave response driven by the ASB slave does not enter the ASB bus when the device select signal does not select the ASB slave. In so doing, when these two predictions are valid, the ASB slave can synchronously drive appropriate slave responses onto the ASB bus without inserting wait states.

US Patent:

6658502, Dec 2, 2003

Filed:

Jun 13, 2000

Appl. No.:

09/593448

Inventors:

Franklyn H. Story - Chandler AZ
Subramanian S. Meiyappan - San Jose CA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1328

US Classification:

710 22, 710 33, 710107, 711105

Abstract:

A novel and sophisticated direct memory access (DMA) controller that can operate in either âfly-byâ mode, âdual-cycleâ mode, or âflow-throughâ mode. The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to choose arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus. An advantage of the present invention is that, because bus master devices are be off-loaded from the host bus, system performance can be dramatically improved. Another advantage is that the present invention provides an easy means for adding more devices to the system.

US Patent:

6993542, Jan 31, 2006

Filed:

Mar 12, 2001

Appl. No.:

09/805333

Inventors:

Subramanian Meiyappan - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1/02

US Classification:

708250, 708252

Abstract:

Truly random numbers are generated with a minimum of extra hardware by taking advantage of the inherent noise in a communication channel. Random numbers can thus be generated without specialized manufacturing requirements and can be incorporated to conventional integrated circuits with minimal additional logic. The random number generation technique offloads the processor from performing extensive generation calculations without the use of the hardware accelerator. This random number generation technique may find application in, e. g. , any network device that participates in a virtual private network or is used to implement electronic commerce.

US Patent:

7100133, Aug 29, 2006

Filed:

Jun 23, 2000

Appl. No.:

09/602422

Inventors:

Subramanian S. Meiyappan - San Jose CA, US
Varaprasad Vajjhala - Campbell CA, US
Edward M. Petryk - Pheonix AZ, US

Assignee:

Koninklijke Philips Electronics N.V - Eindhoven

International Classification:

G06F 17/48

US Classification:

716 5, 716 4

Abstract:

The present invention facilitates automation of system on a chip (SoC) design, manufacture and verification in a convenient and efficient manner. In one embodiment, a SoC netlist builder and verification computer system of the present invention includes a user interface module, a parameter application module, an expert system module and a chip level netlist generation module. The user interface module provides user friendly and convenient interfaces that facilitate easy entry and modification of user selections and parameters. The parameter application module interprets information supplied by the user module and the expert system module and creates directions (e. g. , command lines) passed to other modules for execution. The expert system module analyzes information and automatically provides SoC building and verification data including automated addition of default architectural features, automated insertion of default parameters, and automated input of information to the verification module. The chip level netlist generation module automatically generates a chip level netlist, including the instantiation of internal IC devices and connections between the circuit blocks for internal signals.

US Patent:

8130141, Mar 6, 2012

Filed:

Sep 10, 2009

Appl. No.:

12/557479

Inventors:

Ganesh Pattabiraman - Santa Clara CA, US
Subramanian Meiyappan - Santa Clara CA, US
Arun Raghupathy - Santa Clara CA, US
Hari Sankar - Santa Clara CA, US

Assignee:

Commlabs, Inc. - Sunnyvale CA

International Classification:

G01S 19/46

US Classification:

34235729

Abstract:

Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.