Stewart O Dunlap

US Patent:

6927097, Aug 9, 2005

Filed:

Mar 27, 2003

Appl. No.:

10/401377

Inventors:

Stewart Dunlap - Fair Oaks CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L021/44
H01L023/48

US Classification:

438118, 438108, 438119, 257782, 257783

Abstract:

An underfill material is applied to an electronic component, such as a die, integrated circuit (IC) package, or printed circuit board, prior to mounting of the component upon another packaging element. In an embodiment, the component may be a singulated IC package. Strips of underfill material may be separated from a supply reel and applied to the edges of the IC package. Trays may convey the components to and from automated underfill attach equipment. Assembly methods, as well as application of the package to an electronic assembly and to an electronic system, are also described.

US Patent:

6373268, Apr 16, 2002

Filed:

May 10, 1999

Appl. No.:

09/309195

Inventors:

Stewart O. Dunlap - Folsom CA
Stephen E. Bastear - Folsom CA
Gary M. Meszaros - Roseville CA
Nasser M. Barabi - Lafayette CA
James E. Spooner - Manteca CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3102

US Classification:

324755, 324765, 324754, 324758

Abstract:

A test handling assembly for conjoined integrated circuit dies is disclosed. The assembly has a wafer prober system having a chuck. A panel stage is coupled to the chuck and conjoined integrated circuit dies are coupled to the panel stage. A contactor is provided to communicate with the conjoined integrated circuit dies and the wafer prober system. Other features are disclosed.