Steven A Przybylski

US Patent:

8407395, Mar 26, 2013

Filed:

Aug 22, 2007

Appl. No.:

11/843440

Inventors:

Jin-Ki Kim - Ottawa, CA
HakJune Oh - Kanata, CA
Hong Beom Pyeon - Kanata, CA
Steven Przybylski - Ann Arbor MI, US

Assignee:

Mosaid Technologies Incorporated - Ottawa

International Classification:

G06F 12/00

US Classification:

711100, 711 5, 711103, 711154

Abstract:

A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

US Patent:

8429495, Apr 23, 2013

Filed:

Oct 19, 2010

Appl. No.:

12/907210

Inventors:

Steven Przybylski - Ann Arbor MI, US

Assignee:

MOSAID Technologies Incorporated - Ottawa

International Classification:

G11C 29/00

US Classification:

714763, 714777

Abstract:

A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.

US Patent:

8594110, Nov 26, 2013

Filed:

Jan 11, 2008

Appl. No.:

12/013148

Inventors:

Steven A. Przybylski - Ann Arbor MI, US

Assignee:

MOSAID Technologies Incorporated - Ottawa, Ontario

International Classification:

H04L 12/28

US Classification:

370403

Abstract:

In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.

US Patent:

20080155219, Jun 26, 2008

Filed:

Dec 20, 2006

Appl. No.:

11/613563

Inventors:

Hong Beom PYEON - Kanata, CA
HakJune OH - Kanata, CA
Jin-Ki KIM - Ottawa, CA
Steven A. PRZYBYLSKI - Ann Arbor MI, US

Assignee:

MOSAID TECHNOLOGIES INCORPORATED - Kanata ON

International Classification:

G11C 8/04

US Classification:

711170

Abstract:

A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

US Patent:

20080201548, Aug 21, 2008

Filed:

Feb 19, 2008

Appl. No.:

12/033577

Inventors:

Steven PRZYBYLSKI - Ann Arbor MI, US
Roland SCHUETZ - Ottawa, CA
HakJune OH - Kanata, CA
Hong Beom PYEON - Kanata, CA

Assignee:

MOSAID TECHNOLOGIES INCORPORATED - Kanata

International Classification:

G06F 12/00

US Classification:

711171, 711E12001

Abstract:

A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

US Patent:

20130170298, Jul 4, 2013

Filed:

Feb 26, 2013

Appl. No.:

13/776757

Inventors:

MOSAID TECHNOLOGIES INCORPORATED - Kanata, CA
HakJune OH - Kanata, CA
Hong Beom PYEON - Kanata, CA
Steven PRZYBYLSKI - Ann Arbor MI, US

Assignee:

MOSAID TECHNOLOGIES INCORPORATED - Kanata

International Classification:

G11C 16/10

US Classification:

36518511

Abstract:

A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

US Patent:

20130232393, Sep 5, 2013

Filed:

Apr 18, 2013

Appl. No.:

13/865514

Inventors:

- Ottawa ON, CA
Steven PRZYBYLSKI - Ann Arbor MI, US

Assignee:

MOSAID TECHNOLOGIES INCORPORATED - Ottawa

International Classification:

G11C 29/00

US Classification:

714773, 714763

Abstract:

A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.

US Patent:

49530739, Aug 28, 1990

Filed:

Feb 6, 1986

Appl. No.:

6/827269

Inventors:

John P. Moussouris - Palo Alto CA
Lester M. Crudele - San Jose CA
Steven A. Przybylski - Menlo Park CA

Assignee:

MIPS Computer Systems, Inc. - Mountain View CA

International Classification:

G06F 934
G06F 1210
G06F 1316

US Classification:

364200

Abstract:

A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.