Stephen Lee Sanchez

US Patent:

6825721, Nov 30, 2004

Filed:

Jul 12, 2002

Appl. No.:

10/193871

Inventors:

Stephen J. Sanchez - Tucson AZ
Vadim V. Ivanov - Tuscon AZ
Walter B. Meinel - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330253, 330254, 330258, 327 52

Abstract:

A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

US Patent:

6828856, Dec 7, 2004

Filed:

Oct 31, 2003

Appl. No.:

10/698661

Inventors:

Stephen J. Sanchez - Tucson AZ
Vadim V. Ivanov - Tucson AZ
Walter B. Meinel - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330253, 330257, 330260

Abstract:

A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

US Patent:

6927624, Aug 9, 2005

Filed:

Jun 12, 2003

Appl. No.:

10/461117

Inventors:

Vadim V. Ivanov - Tucson AZ, US
Stephen J. Sanchez - Tucson AZ, US
David M. Jones - Tucson AZ, US
David Spady - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R019/00

US Classification:

330 2, 330 9, 330307

Abstract:

A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins. Instead, the trimming procedure is controlled through sensing of changes in current and/or voltage applied through the existing available pins or bondpads of the devices to determine whether a command for trim programming has occurred. As a result, package-level trimming of the devices can be conducted in standard device packages having low pin count configurations, such as operational amplifiers, instrumentation amplifiers, difference amplifiers, low drop-out regulators, voltage references and other similar types of devices. A device to be trimmed is configured with internal circuitry configured to sense changes in current and/or voltage in the output or supply voltage of the device, and a test system for applying changes in the current and/or voltage through the existing available pins or bondpads of the devices. The internal circuitry can comprise sensing circuitry comprising one or more internal sensors configured to measure current and/or voltage in the output or supply voltage of the device, and can comprise trim programming circuitry for facilitating trim programming of the device.

US Patent:

7029932, Apr 18, 2006

Filed:

Feb 7, 2005

Appl. No.:

11/052121

Inventors:

Daryl T. Hiser - Tucson AZ, US
Stephen J. Sanchez - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/66

US Classification:

438 14, 438 18

Abstract:

Parametric testing of an integrated circuit chip includes pressing first, second, and third contact elements (PRB-) against first, second and third terminals (P), respectively, of the integrated circuit and forcing first, second, and third reference currents (Iref) through first, second, and third circuit paths each including a corresponding ESD diode. Each path includes two of the contact elements, two associated contact resistances, and one of the ESD diodes. First, second, and third voltages (Vm) are measured across the three circuit paths. Three equations representative of the three voltages are simultaneously solved to determine three contact resistances between the various contact elements and integrated circuit terminals. The voltages across the three contact resistances are computed by multiplying them by parametric test currents and are added to or subtracted from measured voltages of the contact elements to obtain accurate values of voltages of the integrated circuit terminals.

US Patent:

7138868, Nov 21, 2006

Filed:

Aug 11, 2004

Appl. No.:

10/917189

Inventors:

Stephen J. Sanchez - Tucson AZ, US
Daryl Hiser - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/45

US Classification:

330256, 330252

Abstract:

A method and circuit for trimming a current source packaged with a device can facilitate trimming of the current source without the need for additional pins or dual function pins, resulting in improved accuracy and/or simplified trimming techniques. An exemplary packaged device is configured with a trimming circuit comprising a current trimming network and a coupling circuit. An exemplary packaged device can comprise any op amp, current or voltage reference, and/or sensor device, and is configured with one or more monitor inputs. An exemplary current trimming network comprises a variable current source and a reference current source, wherein a magnitude of the variable current source can be compared to the magnitude of the reference current source. An exemplary coupling circuit is coupled between the current trimming network and the device and is configured for enabling and disabling connection of an output of the current trimming network and a monitor input of the device. During an exemplary trimming method, the variable current source is configured with a magnitude adjusted to a desired proportion of a magnitude of the reference current source, with the current trimming network configured to produce a current proportional to the difference, sum, or product of the first and second current sources.

US Patent:

20130314009, Nov 28, 2013

Filed:

Mar 13, 2013

Appl. No.:

13/800327

Inventors:

Stephen James Sanchez - Tucson AZ, US
Marc John Kobayashi - Oro Valley AZ, US
Branislav Pjetar - Novi Sad, RS

International Classification:

H02P 6/18

US Classification:

31840006, 31840033

Abstract:

The system discloses structure for synchronizing sequential phase switching in driving a set of stator windings of a multi-phase sensorless brushless permanent magnet DC motor. A drive voltage drives a plurality of the stator windings thereby producing a magnetic field. On an undriven stator winding among the stator windings, a voltage induced by the magnetic field is sampled. The induced voltage changes as a function of a magnetic rotor transitioning across a plurality of angular positions. A first value corresponding to the sampled voltage induced on the currentless winding is compared with a commutation threshold to determine a proper commutation point. The system is switched to a next drive configuration of the sequence when the first value surpasses the threshold.

US Patent:

20130314017, Nov 28, 2013

Filed:

Mar 14, 2013

Appl. No.:

13/827848

Inventors:

Stephen James Sanchez - Tucson AZ, US
Marc John Kobayashi - Oro Valley AZ, US
Branislav Pjetar - Novi Sad, RS
John L. Melanson - Austin TX, US

International Classification:

H02P 6/18

US Classification:

31840033

Abstract:

A system for controlling motor switching in a sensorless BLDC having a stator with three stator windings and a permanent magnet rotor. The system includes a controller unit comprising a control signal generator, a memory device, a processing unit, a signal acquisition device, and an analog-to-digital converter. A power stage controlled by the controller unit has a plurality of switches and drives two windings of the three stator windings with a pulse width modulation signal and leaves one stator of the three stator windings undriven. The processing unit acquires a demodulated measured voltage on the undriven winding. The processing unit calculates a threshold at which the power stage will change which two windings of the three stator windings are driven when the demodulated measured voltage surpasses the threshold.

US Patent:

20130342141, Dec 26, 2013

Filed:

Mar 14, 2013

Appl. No.:

13/826898

Inventors:

Marc John Kobayashi - Tucson AZ, US
Stephen James Sanchez - Tucson AZ, US
John L. Melanson - Austin TX, US
Miroslav Oljaca - Tucson AZ, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H02P 6/18

US Classification:

31840006, 31840033

Abstract:

A system is disclosed for controlling motor switching in a sensorless BLDC motor having a set of three stator windings. A controller unit includes a control signal generator, a memory device, a processing unit, a signal acquisition device, and an analog-to-digital converter. A power stage having a plurality of switches receives a control signal from the control signal generator and a power signal from a power source. The power stage drives two windings of the set of three stator windings with an asymmetric pulse width modulation signal and leaves one stator of the three stator windings undriven. The processing unit acquires a demodulated measured voltage on the undriven winding. The processing unit also communicates with the power stage to change which two windings of the three stator windings are driven when the demodulated measured voltage surpasses a threshold.