Stephanie A Miraglia

US Patent:

7337149, Feb 26, 2008

Filed:

Dec 12, 2000

Appl. No.:

09/735256

Inventors:

Cathy L. Blouin - Franklin VT, US
Carolyn S. Camisa - Essex Junction VT, US
Stephanie A. Miraglia - Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06Q 99/00

US Classification:

705400, 705 1, 700121

Abstract:

A method and structure for predicting semiconductor product costs at a fabricator entailing a storage medium which includes a database of historical critical dimensions and historical critical groundrules correlated to cost functions at the fabricator. The user interface has user inputs for new design parameters and new critical groundrules associated with a new device to be produced at the fabricator and a computer adapted to receive the user inputs, extract data from the storage medium, and compute semiconductor costs for the new device. The historical critical dimensions and the new critical dimensions are gate dimensions and the new critical dimensions are smaller than the historical critical dimensions. This device includes a future technology generation. Fabrication hardware and fabrication methods for producing the future technology generation are unknown and the relationships comprise base models and models that include options.

US Patent:

62497766, Jun 19, 2001

Filed:

Sep 22, 1998

Appl. No.:

9/158268

Inventors:

Stanislav P. Bajuk - Austin TX
Cathy L. Blouin - Franklin VT
Gregory A. Blunt - Essex Junction VT
Gary D. Boldman - Jericho VT
Robert C. Juba - Manasas VA
Daniel A. McAuliffe - Burlington VT
Peter J. Miller - Essex Junction VT
Stephanie A. Miraglia - Burlington VT
Thomas C. Richardson - Huntington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1760

US Classification:

705400

Abstract:

A method of, computer system for, and computer program product for causally relating costs to products, including relating costs to a wafer having semiconductor chips comprising identifying resource costs for manufacturing the wafer including identifying equipment costs, computing load factors for each of the resource costs (the computing load factors for the equipment costs comprising determining a number of exposure fields on the wafer, computing a raw processing time for the wafer based on the number of exposure fields, and determining a percentage the raw processing time represents of a manufacturing time period on an equipment element, the equipment element having the equipment costs), producing weighted resource costs based on the resource costs and the load factors, (the producing weighted resource costs for the equipment costs comprising multiplying the equipment costs by the percentage), summing the weighted resource costs for the wafer, determining a volume of the wafer manufactured, and dividing the weighted resource costs by the volume to produce a weighted cost per wafer.

US Patent:

63245272, Nov 27, 2001

Filed:

Sep 22, 1998

Appl. No.:

9/158478

Inventors:

Stanislav P. Bajuk - Austin TX
Cathy L. Blouin - Franklin VT
Gregory A. Blunt - Essex Junction VT
Gary D. Boldman - Jericho VT
Robert C. Juba - Manassas VA
Daniel A. McAuliffe - Burlington VT
Peter J. Miller - Essex Junction VT
Stephanie A. Miraglia - Burlington VT
Thomas C. Richardson - Huntington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1760

US Classification:

705400

Abstract:

A method of, computer system for, and computer program product for causally relating costs to products comprises, identifying resource costs for manufacturing the product, computing load factors for each of the resource costs, producing weighted resource costs based on the resource costs and the load factors, summing the weighted resource costs for the product, determining a volume of the product manufactured, and dividing the weighted resource costs by the volume to produce a weighted cost per product.