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Sriram Badrinarayanan

age ~46

from Fremont, CA

Also known as:
  • Spiram Badrinarayanan
  • Criram Badrinarayanan
  • Sriram Badrinaraya
  • Sriram Badrinarayan
Phone and address:
309 Anza St, Fremont, CA 94539

Sriram Badrinarayanan Phones & Addresses

  • 309 Anza St, Fremont, CA 94539
  • Cupertino, CA
  • 1550 Iron Point Rd, Folsom, CA 95630 • 916 608-9438
  • Edwardsville, IL
  • 1550 Iron Point Rd, Folsom, CA 95630 • 916 806-3941

Work

  • Company:
    Intel corporation
    2003 to 2007
  • Position:
    I and o design engineer - cpu-mch links

Education

  • Degree:
    Masters
  • School / High School:
    Southern Illinois University Edwardsville
    1999 to 2001
  • Specialities:
    Electrical Engineering

Skills

Analog Circuit Design • Mixed Signal • Cmos • Integrated Circuit Design • Serdes • Vlsi • Analog • Integrated Circuits • Circuit Design • Silicon • Semiconductors • Serdes Design

Industries

Semiconductors

Resumes

Sriram Badrinarayanan Photo 1

Senior Serdes Designer

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Location:
Cupertino, CA
Industry:
Semiconductors
Work:
Intel Corporation 2003 - 2007
I and O Design Engineer - Cpu-Mch Links

Intel Corporation 2003 - 2007
Senior Serdes Designer

Intel Corporation 2001 - 2003
Circuit Designer- Chipset Group
Education:
Southern Illinois University Edwardsville 1999 - 2001
Masters, Electrical Engineering
Skills:
Analog Circuit Design
Mixed Signal
Cmos
Integrated Circuit Design
Serdes
Vlsi
Analog
Integrated Circuits
Circuit Design
Silicon
Semiconductors
Serdes Design

Us Patents

  • Duty Cycle Rejecting 2:1 Serializing Mux For Output Data Drivers

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  • US Patent:
    20070157048, Jul 5, 2007
  • Filed:
    Dec 30, 2005
  • Appl. No.:
    11/322681
  • Inventors:
    Alexander Levin - Port Orchard WA, US
    Sriram Badrinarayanan - Folsom CA, US
    Chris Matthews - Folsom CA, US
  • International Classification:
    G06F 1/12
    G06F 13/42
  • US Classification:
    713400000
  • Abstract:
    A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. The second clocking signal is 180 degrees out of phase with the first clocking signal to sample the first input data stream in the first unit interval of an output data stream and the second input data stream in the second unit interval of the output data stream. Consequently, a serialized output data stream is driven at twice the frequency of both the first and the second input data streams, including logical information from the first and second input data streams every period of the output data stream.

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Sriram Badrinarayanan Photo 2

Sriram Badrinarayanan

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Sriram Badrinarayanan Photo 3

Sriram Badrinarayanan

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Friends:
Yashwanth Naren, Gokul Muralidharan, Avinash Bharatwaj

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