Sriraj G Manavalan

US Patent:

20130049110, Feb 28, 2013

Filed:

Aug 23, 2011

Appl. No.:

13/215981

Inventors:

Kuo Chen Wang - Boise ID, US
Sriraj Manavalan - Boise ID, US
Wei Ming Liao - Taipei, TW

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257334, 257329, 438270, 257E2141, 257E29262

Abstract:

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

US Patent:

20150236023, Aug 20, 2015

Filed:

Apr 29, 2015

Appl. No.:

14/699350

Inventors:

- Boise ID, US
Sriraj Manavalan - Boise ID, US
Wei Ming Liao - Rueishan Township, TW

International Classification:

H01L 27/108

Abstract:

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.