Srinagesh G Loke
age ~51
from Austin, TX
- Also known as:
-
- Srina G Loke
- Frinagesh Loke
- Loke Srinagesh
- Phone and address:
-
10617 Straw Flower Dr, Austin, TX 78733
512 257-1485
Srinagesh Loke Phones & Addresses
- 10617 Straw Flower Dr, Austin, TX 78733 • 512 257-1485
- 13516 Bolivia Dr, Austin, TX 78729 • 512 257-1485 s
- 10167 Straw Flower Dr, Austin, TX 78733
- 7616 Covered Bridge Dr, Austin, TX 78736 • 512 257-1485
- 6000 Shepherd Mountain Cv, Austin, TX 78730 • 512 502-9247
- Manchaca, TX
- Driftwood, TX
- Bryan, TX
- College Station, TX
Name / Title
Company / Classification
Phones & Addresses
President
VERIRIGHT INC
Business Consulting Services
Business Consulting Services
7616 Covered Brg Dr, Austin, TX 78736
DIRECTOR, Director
OCTASCIENT L L C
7616 Covered Brg Dr, Austin, TX 78736
13516 Bolivia Dr, Austin, TX 78729
13516 Bolivia Dr, Austin, TX 78729
Director
Octascient, LLC
13516 Bolivia Dr, Austin, TX 78729
Resumes
Design Verification Manager
view sourceLocation:
Austin, TX
Industry:
Semiconductors
Work:
Qualcomm since Nov 2009
Staff Verification Engineer
Qualcomm Jun 2009 - Nov 2009
Verification Consultant
Qualcomm Apr 2008 - Jan 2009
Verification Consultant
Qualcomm Mar 2006 - Mar 2008
Verification Consultant
SigmaTel Inc Jan 2005 - Mar 2006
Member of Technical Staff
Staff Verification Engineer
Qualcomm Jun 2009 - Nov 2009
Verification Consultant
Qualcomm Apr 2008 - Jan 2009
Verification Consultant
Qualcomm Mar 2006 - Mar 2008
Verification Consultant
SigmaTel Inc Jan 2005 - Mar 2006
Member of Technical Staff
Education:
Texas A&M University 1996 - 1998
M.S, Electrical Engineering Jawaharlal Nehru Technological University 1992 - 1996
B. Tech, Electronics & Communication Engineering All Saints' High School
M.S, Electrical Engineering Jawaharlal Nehru Technological University 1992 - 1996
B. Tech, Electronics & Communication Engineering All Saints' High School
Skills:
Systemverilog
Verilog
Functional Verification
Soc
Simulations
Processors
Asic
Debugging
Perl
Microprocessors
Formal Verification
Digital Signal Processors
Arm
Uvm
Vlsi
Integrated Circuit Design
Microarchitecture
Hardware Architecture
Modelsim
Vmm
Computer Architecture
Vera
Open Verification Methodology
Dsp
Ahb
Vcs
Digital Design
Hardware Verification
I2C
Hardware Design
Logic Design
Low Power Design
Assertion Based Verification
Rtl Verification
Power Management
Assembly Language
Perl Script
Gnu Make
Management
Verilog
Functional Verification
Soc
Simulations
Processors
Asic
Debugging
Perl
Microprocessors
Formal Verification
Digital Signal Processors
Arm
Uvm
Vlsi
Integrated Circuit Design
Microarchitecture
Hardware Architecture
Modelsim
Vmm
Computer Architecture
Vera
Open Verification Methodology
Dsp
Ahb
Vcs
Digital Design
Hardware Verification
I2C
Hardware Design
Logic Design
Low Power Design
Assertion Based Verification
Rtl Verification
Power Management
Assembly Language
Perl Script
Gnu Make
Management
Interests:
Science and Technology
Children
Education
Children
Education
Languages:
English
Telugu
Hindi
Telugu
Hindi
Certifications:
Becoming Indistractable
Senior Verification Engineer
view sourceLocation:
6000 Parmer Ln west, Austin, TX 78727
Industry:
Semiconductors
Work:
Sigmatel
Senior Verification Engineer
Senior Verification Engineer
Plaxo
Srinagesh Loke
view sourceAustin, TX- Founder of VeriRight (Verification Done Right) Inc - a verification and design consulting/contracting business in Austin, TX
- Is open to travel/relocate for... - Founder of VeriRight (Verification Done Right) Inc - a verification and design consulting/contracting business in Austin, TX
- Is open to travel/relocate for a full-time/contract position in Design Verification
- Senior Verification Engineer currently consulting/contracting in Austin, TX
...
Googleplus
Srinagesh Loke
Lived:
Austin, TX
Hyderabad, India
Hyderabad, India
Youtube
Srinagesh Loke
view sourceGet Report for Srinagesh G Loke from Austin, TX, age ~51