Sridhar Jayaraman

US Patent:

20070022342, Jan 25, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/174198

Inventors:

Silvio Picano - Hillsboro OR, US
Sridhar Jayaraman - Portland OR, US
Peter DesRosier - Portland OR, US
James Chung - Milpitas CA, US

International Classification:

G01R 31/28

US Classification:

714727000

Abstract:

An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.