Son G Nguyen

US Patent:

6495233, Dec 17, 2002

Filed:

Jul 5, 2000

Appl. No.:

09/609994

Inventors:

Inna Shmurun - Foster City CA
Scott Hendrickson - Brentwood CA
Gwendolyn Jones - Roseville CA
Shankar Venkataraman - Santa Clara CA
Son T. Nguyen - San Jose CA
I-Chun Eugenia Liu - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B32B 302

US Classification:

428 641, 428 661, 428 666, 118715, 118718, 118720, 118713, 118723 T, 118723 IR, 118723 E, 118723 R, 118723 ER, 118724, 118725

Abstract:

A lid assembly for a semiconductor processing apparatus having at least two chambers comprises a lid plate having a first side and a second side and a plasma generation source mounted to the first side of the lid plate. Additionally, at least two gas boxes are coupled to the first side of the lid of the lid plate, and a divider is coupled between the plasma generation source and the at least two gas boxes.

US Patent:

6714903, Mar 30, 2004

Filed:

Jul 10, 1998

Appl. No.:

09/113995

Inventors:

Sudhakar R. Gouravaram - Fremont CA
Son Nguyen - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1710

US Classification:

703 19, 716 6, 716 10, 716 2

Abstract:

A cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit. The invention is also directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells. According to this aspect of the invention, one of the cells obtained from the cell library, referred to as a combined cell, includes (1) a signal processing circuit; (2) a buffer circuit for buffering a signal external to the integrated circuit in which the combined cell is to be included; and (3) layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.

US Patent:

D539572, Apr 3, 2007

Filed:

Jun 3, 2005

Appl. No.:

29/231413

Inventors:

Son K. Nguyen - Sacramento CA, US

International Classification:

0606

US Classification:

D 6501

US Patent:

7223323, May 29, 2007

Filed:

Jul 8, 2003

Appl. No.:

10/616284

Inventors:

Michael X. Yang - Palo Alto CA, US
Ming Xi - Palo Alto CA, US
Russell C. Ellwanger - San Jun Bautista CA, US
Eric B. Britcher - Rancho Cucamonga CA, US
Bernardo Donoso - San Jose CA, US
Lily L. Pang - Fremont CA, US
Svetlana Sherman - San Jose CA, US
Henry Ho - San Jose CA, US
Anh N. Nguyen - Milpitas CA, US
Alexander N. Lerner - San Jose CA, US
Allen L. D'Ambra - Burlingame CA, US
Arulkumar Shanmugasundram - Sunnyvale CA, US
Tetsuya Ishikawa - Saratoga CA, US
Yevgeniy Rabinovich - Fremont CA, US
Dmitry Lubomirsky - Cupertino CA, US
Son T. Nguyen - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C25B 9/12
C35D 3/38
B08B 3/02

US Classification:

204242, 2042288, 2042751, 205157, 205191, 134 26, 134148, 134151, 134153

Abstract:

Embodiments of the invention generally provide an electrochemical plating system. The plating system includes a substrate loading station positioned in communication with a mainframe processing platform, at least one substrate plating cell positioned on the mainframe, at least one substrate bevel cleaning cell positioned on the mainframe, and a stacked substrate annealing station positioned in communication with at least one of the mainframe and the loading station, each chamber in the stacked substrate annealing station having a heating plate, a cooling plate, and a substrate transfer robot therein.

US Patent:

7280313, Oct 9, 2007

Filed:

Apr 30, 2004

Appl. No.:

10/837386

Inventors:

Jeffrey S. Lille - Sunnyvale CA, US
Son Van Nguyen - Los Gatos CA, US
Hugo Alberto Emilio Santini - San Jose CA, US

Assignee:

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam

International Classification:

G11B 5/17
G11B 5/127

US Classification:

360123, 2960323, 2960325, 2960318

Abstract:

A a method for fabricating a structure, such as a magnetic head, having two coplanar metallic features of different compositions, both deposited on their own seed layers. The features may be made tall relative to their widths (ie. have a high aspect ratio), and are also very closely spaced. Only a single high-definition, critically aligned photolithographic procedure is used to create the critical structures, avoiding any problem with aligning features produced by multiple procedures. The method is applied to the production of the write structure of a magnetic read/write head, where a portion of the pole structure and the inductive coils are fabricated in the same plane with a close spacing and both having a vertical aspect ratio of more than about 2:1.

US Patent:

7680047, Mar 16, 2010

Filed:

Nov 22, 2005

Appl. No.:

11/284483

Inventors:

Sravan Vadlakonda - Sunnyvale CA, US
Son D. Nguyen - San Jose CA, US
Manjunath S. Bangalore - San Jose CA, US
Vikram Khurana - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 1/16

US Classification:

370235, 370389, 3702301

Abstract:

A Real-Time Protocol (RTP) source node of a network operates to send a first data packet of a first size to a destination node over a path of the network that includes a plurality of intermediate nodes, at least one of the intermediate nodes having a maximum transmission unit (MTU) size smaller than the first size such that fragmentation of the first data packet occurs. The destination node sends back to the source node a RTCP report that includes a number of fragments received and a largest minimum data packet size. In response, the source node sends subsequent data packets having a second size less than or equal to the largest data packet size of the fragments. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

US Patent:

8094569, Jan 10, 2012

Filed:

Dec 5, 2008

Appl. No.:

12/329115

Inventors:

Naveen Gunukula - Sunnyvale CA, US
Jeslin Puthenparambil - San Jose CA, US
Son Nguyen - San Jose CA, US
Byung Lim - Fremont CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 3/14

US Classification:

370242, 370248

Abstract:

A router is provided. The router includes a primary interface, a backup interface, a processor, and a memory. The primary interface and backup interface may be used to communicate with a network switch. The router may be configured to determine whether the primary interface is stable. The primary interface is stable when the primary interface may be used to exchange information with a network switch over a primary network segment. The router may be configured to activate the primary interface when the primary interface is determined to be stable. The router may also be configured to activate the backup interface when the primary interface is determined to be not stable. The backup interface may be activated for the exchange of information with the network switch.

US Patent:

8183132, May 22, 2012

Filed:

Mar 31, 2010

Appl. No.:

12/751692

Inventors:

Sandeep Nijhawan - Los Altos CA, US
Brian H. Burrows - San Jose CA, US
Tetsuya Ishikawa - Saratoga CA, US
Olga Kryliouk - Sunnyvale CA, US
Anand Vasudev - San Francisco CA, US
Jie Su - Santa Clara CA, US
David H. Quach - San Jose CA, US
Anzhong Chang - San Jose CA, US
Yuriy Melnik - Santa Clara CA, US
Harsukhdeep S. Ratia - Santa Clara CA, US
Son T. Nguyen - San Jose CA, US
Lily Pang - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/20
H01L 21/00

US Classification:

438478, 438503, 438507, 438 46

Abstract:

The present invention generally provides apparatus and methods for forming LED structures. One embodiment of the present invention provides a method for fabricating a compound nitride structure comprising forming a first layer comprising a first group-III element and nitrogen on substrates in a first processing chamber by a hydride vapor phase epitaxial (HVPE) process or a metal organic chemical vapor deposition (MOCVD) process, forming a second layer comprising a second group-III element and nitrogen over the first layer in a second processing chamber by a MOCVD process, and forming a third layer comprising a third group-III element and nitrogen over the second layer by a MOCVD process.