Sivakumar Doraiswamy from 3670 Peacock Ct APT 13, Santa Clara, CA 95051, age 54

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Driver Calibration Methods And Circuits
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US Patent:

7389194, Jun 17, 2008
Filed:

Jul 6, 2005
Appl. No.:

11/176876
Inventors:

Huy M. Nguyen - San Jose CA, US
Vijay Gadde - Cupertino CA, US
Sivakumar Doraiswamy - San Jose CA, US
Assignee:

Rambus Inc. - Los Altos CA
International Classification:

H03F 3/04
G01R 35/00
US Classification:

702107, 702 65, 702 57, 330250
Abstract:

Described are amplifiers that facilitate high-speed communication with calibrated drive strength and tennination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be updated while signals (e. g, clock or data) are transmitted. Some embodiments identify elements in a high-impedance state by examining incoming signals.

Driver Calibration Methods And Circuits
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US Patent:

8237468, Aug 7, 2012
Filed:

Aug 3, 2010
Appl. No.:

12/849177
Inventors:

Huy M. Nguyen - San Jose CA, US
Vijay Gadde - Cupertino CA, US
Sivakumar Doraiswamy - San Jose CA, US
Assignee:

Rambus Inc. - Sunnnyvale CA
International Classification:

H03K 19/0175
US Classification:

326 82, 326 30, 326 83, 326 87, 327109, 327112, 330255
Abstract:

Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e. g. , clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Dynamic Circuit Using Exclusive States
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US Patent:

7028069, Apr 11, 2006
Filed:

Nov 27, 2001
Appl. No.:

09/996865
Inventors:

Edward T. Pak - Saratoga CA, US
Sivakumar Doraiswamy - Sunnyvale CA, US
Assignee:

Raza Microelectronics Inc. - Cupertino CA
International Classification:

G06F 7/50
US Classification:

708710, 708711
Abstract:

The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.

Memory Controller For Strobe-Based Memory Systems
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US Patent:

20230105557, Apr 6, 2023
Filed:

Sep 15, 2022
Appl. No.:

17/945956
Inventors:

- San Jose CA, US
Sivakumar Doraiswamy - San Jose CA, US
Benedict Lau - San Jose CA, US
International Classification:

G11C 11/4076
G06F 13/16
G06F 13/40
G11C 8/18
G11C 7/22
G11C 11/4063
G11C 11/4072
G11C 11/4096
Abstract:

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Memory Controller For Strobe-Based Memory Systems
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US Patent:

20210134347, May 6, 2021
Filed:

Nov 19, 2020
Appl. No.:

16/953196
Inventors:

- San Jose CA, US
Sivakumar Doraiswamy - San Jose CA, US
Benedict Lau - San Jose CA, US
International Classification:

G11C 11/4076
G06F 13/16
G06F 13/40
G11C 8/18
G11C 7/22
G11C 11/4063
G11C 11/4072
G11C 11/4096
Abstract:

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Memory Controller For Strobe-Based Memory Systems
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US Patent:

20200211619, Jul 2, 2020
Filed:

Dec 23, 2019
Appl. No.:

16/726048
Inventors:

- Sunnyvale CA, US
Sivakumar Doraiswamy - San Jose CA, US
Benedict Lau - San Jose CA, US
International Classification:

G11C 11/4076
G06F 13/16
G06F 13/40
G11C 8/18
G11C 7/22
G11C 11/4063
G11C 11/4072
G11C 11/4096
Abstract:

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Memory Controller For Strobe-Based Memory Systems
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US Patent:

20190362766, Nov 28, 2019
Filed:

Jun 7, 2019
Appl. No.:

16/435308
Inventors:

- Sunnyvale CA, US
Sivakumar Doraiswamy - San Jose CA, US
Benedict Lau - San Jose CA, US
International Classification:

G11C 11/4076
G11C 11/4063
G11C 8/18
G06F 13/40
G11C 7/22
G11C 11/4096
G11C 11/4072
G06F 13/16
Abstract:

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Memory Controller For Strobe-Based Memory Systems
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US Patent:

20180277193, Sep 27, 2018
Filed:

Feb 15, 2018
Appl. No.:

15/898034
Inventors:

- Sunnyvale CA, US
Sivakumar Doraiswamy - San Jose CA, US
Benedict Lau - San Jose CA, US
International Classification:

G11C 11/4076
G11C 11/4072
G11C 11/4096
Abstract:

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.