Siufu Chiu

US Patent:

20110149666, Jun 23, 2011

Filed:

Dec 23, 2009

Appl. No.:

12/645623

Inventors:

Fatih Hamzaoglu - Portland OR, US
Gunjan H. Pandya - Portland OR, US
Siufu Chiu - San Jose CA, US
Kevin Zhang - Portland OR, US

International Classification:

G11C 7/00
G11C 5/14

US Classification:

365203, 365227

Abstract:

Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.