Shukur M Pathan

US Patent:

8516196, Aug 20, 2013

Filed:

Jun 1, 2012

Appl. No.:

13/486091

Inventors:

Prashant Jain - San Jose CA, US
Yoganand Chillarige - Sunnyvale CA, US
Sandip Das - Belmont CA, US
Shukur Moulali Pathan - San Jose CA, US
Srinivasan R. Iyengar - Fremont CA, US
Sanjay Patel - San Ramon CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 12/00

US Classification:

711122, 711118, 711130, 711131

Abstract:

A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.

US Patent:

20110185125, Jul 28, 2011

Filed:

Jan 27, 2010

Appl. No.:

12/694877

Inventors:

Prashant Jain - San Jose CA, US
Yoganand Chillarige - Sunnyvale CA, US
Sandip Das - Belmont CA, US
Shukur Moulali Pathan - San Jose CA, US
Srinivasan R. Iyengar - Fremont CA, US
Sanjay Patel - San Ramon CA, US

International Classification:

G06F 12/08
G06F 12/00
G06F 13/28

US Classification:

711122, 711141, 711130, 710 22, 711E12001, 711E12026, 711E12038, 711E12024

Abstract:

A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.