Shreekant S Thakkar

Author:

Shreekant S. Thakkar

ISBN #:

0792390741

Author:

Shreekant Thakkar

ISBN #:

0792392191

US Patent:

6425073, Jul 23, 2002

Filed:

Mar 13, 2001

Appl. No.:

09/805280

Inventors:

Patrice Roussel - Portland OR
Glenn J. Hinton - Portland OR
Shreekant S. Thakkar - Portland OR
Brent R. Boswell - Beaverton OR
Karol F. Menezes - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

712221, 712242

Abstract:

A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

US Patent:

6434650, Aug 13, 2002

Filed:

Oct 21, 1998

Appl. No.:

09/176571

Inventors:

Jeff C. Morris - Cornelius OR
Robert J. Greiner - Beaverton OR
Narayana S. Iyer - Davis CA
Pranav H. Mehta - Chandler AZ
Shreekant Thakkar - Portland OR
Peter Ruscito - Falsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710110, 710 72, 710107, 710113, 710303

Abstract:

An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer. The uni-directional clock line synchronously clocks both the bi-directional data and command bus and the bi-directional control line.

US Patent:

6463494, Oct 8, 2002

Filed:

Dec 30, 1998

Appl. No.:

09/223302

Inventors:

Jeff Morriss - Cornelius OR
Pranav Mehta - Chandler AZ
Narayanan Iyer - Davis CA
Robert Greiner - Beaverton OR
Peter J. Ruscito - Folsom CA
Shreekant Thakkar - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

710305, 710110

Abstract:

A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

US Patent:

6480868, Nov 12, 2002

Filed:

Apr 27, 2001

Appl. No.:

09/844728

Inventors:

Mohammad A.F. Abdallah - Folson CA
Hsien-Cheng E. Hsieh - Gold River CA
Thomas R. Huff - Portland OR
Vladimir Pentkovski - Folsom CA
Patrice Roussel - Portland OR
Shreekant S. Thakkar - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7100

US Classification:

708204, 712221

Abstract:

A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

US Patent:

6502115, Dec 31, 2002

Filed:

Apr 27, 2001

Appl. No.:

09/845610

Inventors:

Mohammad A. F. Abdallah - Folsom CA
Hsien-Cheng E. Hsieh - Gold River CA
Thomas R. Huff - Portland OR
Vladimir Pentkovski - Folsom CA
Patrice Roussel - Portland OR
Shreekant S. Thakkar - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 700

US Classification:

708204, 712220

Abstract:

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

US Patent:

6507904, Jan 14, 2003

Filed:

Mar 31, 2000

Appl. No.:

09/541477

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - Foster City CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 944

US Classification:

712229, 711152, 709100

Abstract:

A technique is provided to execute isolated instructions according to an embodiment of the present invention. An execution unit executes an isolated instruction in a processor operating in a platform. The processor is configured in one of a normal execution mode and an isolated execution mode. A parameter storage containing at least one parameter to support execution of the isolated instruction when the processor is configured in the isolated execution mode.

US Patent:

6633963, Oct 14, 2003

Filed:

Jul 18, 2000

Appl. No.:

09/618489

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - San Mateo CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1206

US Classification:

711163, 711153, 711152, 711170, 711173

Abstract:

A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.

US Patent:

6678825, Jan 13, 2004

Filed:

Jul 18, 2000

Appl. No.:

09/618738

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - San Mateo CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1760

US Classification:

713200, 711152, 711163, 710200

Abstract:

The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated area of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction.