Shinji Bessho

US Patent:

8068379, Nov 29, 2011

Filed:

Mar 31, 1998

Appl. No.:

09/050946

Inventors:

Tsutomu Takahashi - Tachikawa, JP
Kouji Arai - Kodaira, JP
Yasushi Takahashi - Urawa, JP
Atsuya Tanaka - Tokorozawa, JP
Shunichi Sukegawa - Plano TX, US
Shinji Bessho - Plano TX, US
Masayuki Hira - Dallas TX, US

Assignee:

Hitachi, Ltd. - Tokyo
Texas Instruments Inc. - Dallas TX

International Classification:

G11C 8/00

US Classification:

36523003, 36523006, 365 63

Abstract:

A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

US Patent:

60349204, Mar 7, 2000

Filed:

Nov 24, 1998

Appl. No.:

9/198816

Inventors:

Shunichi Sukegawa - Plano TX
Shinji Bessho - Plano TX
Tadashi Tachibana - Miho-mura, JP
Hiroyuki Yoshida - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 800

US Classification:

3652335

Abstract:

A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V. sub. BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V. sub.

US Patent:

60317795, Feb 29, 2000

Filed:

Apr 10, 1998

Appl. No.:

9/058147

Inventors:

Yasushi Takahashi - Urawa, JP
Tsutomu Takahashi - Tokyo, JP
Kouji Arai - Kodaira, JP
Tsugio Takahashi - Hamura, JP
Shunichi Sukegawa - Plano TX
Shinji Bessho - Plano TX
Masayuki Hira - Dallas TX

Assignee:

Hitachi, Ltd. - Tokyo
Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365226

Abstract:

Described herein is a dynamic memory. An N channel type voltage clamp MOSFET is provided which has a drain supplied with a supply voltage supplied from an external terminal, a gate to which a boosted constant voltage is applied, and a source which outputs a constant voltage. The clamp voltage outputted from the source of the voltage clamp MOSFET is supplied to a common source line for each of P channel type amplification MOSFETs constituting a sense amplifier via a P channel type first power MOSFET switch-controlled by a sense amplifier activation signal, as a voltage for operating the sense amplifier. Further, the constant voltage outputted from the source of the voltage clamp MOSFET is supplied to an N-well region in which the P channel type first power MOSFET and the P channel type MOSFETs constituting the sense amplifier are formed, as a bias voltage.

US Patent:

60021624, Dec 14, 1999

Filed:

Jun 4, 1998

Appl. No.:

9/090721

Inventors:

Yasushi Takahashi - Urawa, JP
Tsutomu Takahashi - Tachikawa, JP
Koji Arai - Kodaira, JP
Shinji Bessho - Plano TX
Shunichi Sukegawa - Plano TX
Masayuki Hira - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2972

US Classification:

257544

Abstract:

Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect. Also, in the P well 16, in regard to the N-type MOS transistors of the sense amplifiers that undergo the substrate bias effect due to the back bias VBB, the threshold voltage is designed to a low value so as to cancel that bias effect.

US Patent:

59700106, Oct 19, 1999

Filed:

Jul 17, 1998

Appl. No.:

9/116915

Inventors:

Masayuki Hira - Dallas TX
Shunichi Sukegawa - Plano TX
Shinji Bessho - Plano TX
Yasushi Takahashi - Urama, JP
Koji Arai - Kodaira, JP
Tsutomu Takahashi - Tachikawa, JP
Tsugio Takahashi - Hamura, JP

Assignee:

Texas Instruments Incorporated - Dallas TX
Hitachi, Ltd.

International Classification:

G11C 700

US Classification:

365226

Abstract:

Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines. The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the wiring length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the wiring between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

US Patent:

60976489, Aug 1, 2000

Filed:

Apr 24, 1998

Appl. No.:

9/066579

Inventors:

Shinji Bessho - Plano TX
Shunichi Sukegawa - Plano TX
Masayuki Hira - Dallas TX
Yasushi Takahashi - Urawa, JP
Tsutomu Takahashi - Tachikawa, JP
Koji Arai - Kodaira, JP

Assignee:

Texas Instruments Incorporated - Dallas TX
Hitachi, Ltd. - Tokyo

International Classification:

G11C 700

US Classification:

365203

Abstract:

An equalizer control line BLEQ shared by all sense amplifiers SA in each row in each submat SM is connected to a first equalizer control line driver consisting of P-type MOS transistors installed at the left end of the submat SM and is connected to several second equalizer control line drivers 32 consisting of N-type MOS transistors installed by dividing in a cross area 16 of each row through which the equalizer control line BLEQ passes. In order to turn on the equalizers of the bit line pair connected to each sense amplifier S, the first equalizer control line driver is operated to drive the equalizer control line BLEQ to the H level potential. In order to turn off the equalizers of each bit line pair, the second equalizer control line drivers 32 are operated to drive the equalizer control line BLEQ to the L level potential. The first and second equalizer control line drivers are complementarily operated. One of them is driven, and the other is turned off (blocked).

US Patent:

60494999, Apr 11, 2000

Filed:

Jul 17, 1998

Appl. No.:

9/118169

Inventors:

Shunichi Sukegawa - Plano TX
Shinji Bessho - Plano TX
Masayuki Hira - Dallas TX
Yasushi Takahashi - Urawa, JP
Tsutomu Takahashi - Tachikawa, JP
Koji Arai - Kodaira, JP

Assignee:

Texas Instruments Incorporated - Dallas TX
Hitachi, Ltd. - Tokyo

International Classification:

G11C 700

US Classification:

365228

Abstract:

To reduce both the noise level according to separation or short-circuitng of the electrical supply line of the sense amplifiers and the electrical supply line of the word line driving circuit and to effectively prevent destruction of the stored data in the nonselecteded memory cell. Electrical supply line (Vssw) of the power supply voltage with respect to word line driving circuit (SWD) and electrical supply line (Vssa) of power supply voltage with respect to sense amplifier driving circuit (SAD) are arranged separately in memory array area 2 (e. g. , in the space in the row direction of memory array (SMAx,y)) and connected to shared electrical supply wiring (Vsso) within peripheral circuit area 3.