Sherman Susan A Weisbrod

US Patent:

57811393, Jul 14, 1998

Filed:

Mar 19, 1996

Appl. No.:

8/618222

Inventors:

Sherman Weisbrod - Skillman NJ

Assignee:

Thomson multimedia S.A. - Boulogne

International Classification:

H03M 166

US Classification:

341150

Abstract:

In a switched capacitor type digital-to-analog (D/A) converter, a group of n bits of the binary word are applied to n parallel branches of the D/A converter, respectively. In a given branch, the corresponding bit is applied to a control terminal of a corresponding switch associated with a corresponding switched capacitor. Depending on the logic level of the bit, the switched capacitor is charged to a reference voltage or remains discharged. Then, the switched capacitor of the given branch is coupled by a transfer switch in parallel with a summing capacitor to provide for charge redistribution. The capacitances of the switched capacitor and of the summing capacitor are equal. The time allocated for either discharging the switched capacitor or charge redistribution is made shorter than the time allocated for charging the capacitor. Charging/discharging the capacitor is accomplished via a common transistor.

US Patent:

56869355, Nov 11, 1997

Filed:

Mar 6, 1995

Appl. No.:

8/399012

Inventors:

Sherman Weisbrod - Skillman NJ

Assignee:

Thomson Consumer Electronics, S.A. - Courbevoie

International Classification:

G09G 336

US Classification:

345100

Abstract:

A video display driver applies a video signal to column electrodes of a liquid crystal display. The display driver includes a reference ramp generator and column data line drivers. A reference ramp signal is combined with the video signal and applied to an input of a comparator. The comparator controls a first transistor that couples a data ramp signal to a given column of pixels. The first transistor at least partially initializes a voltage developed in the given column of pixels prior to an instant when the data ramp signal begins upramping. A second transistor that is coupled in parallel with the first transistor insures that the column voltage is fully initialized.

US Patent:

43261515, Apr 20, 1982

Filed:

Dec 16, 1980

Appl. No.:

6/216908

Inventors:

Sherman Weisbrod - Somerville NJ

Assignee:

RCA Corporation - New York NY

International Classification:

H01J 2974

US Classification:

315410

Abstract:

A triangular waveform generator for applying a scanning waveform to the scan electrodes of a modular display device includes a constant current source and a coupling transformer. A charge storage capacitor is coupled to the secondary of the coupling transformer. A squarewave generator actuates a switch to alternately charge the capacitor in opposite directions resulting in the generation of the triangular waveform. Discharge means is provided to protect the switch from high voltages which could be developed when the generator is turned off.

US Patent:

56730632, Sep 30, 1997

Filed:

Mar 6, 1995

Appl. No.:

8/399011

Inventors:

Sherman Weisbrod - Skillman NJ

Assignee:

Thomson Consumer Electronics, S.A. - Courbevoie

International Classification:

G02F 1133

US Classification:

345100

Abstract:

A video display driver applies a video signal to pixels arranged in columns and rows of a liquid crystal display. A given column or data line driver includes a field effect transistor that operates as a comparator. The comparator is responsive to the video signal and to a reference ramp signal. A triggering voltage of the comparator is automatically and periodically adjusted. A drain voltage of the transistor that is equal to a threshold voltage of the transistor is developed in a stray capacitance, during the automatic adjustment period. A pulse signal, is coupled via the capacitance to increase the drain voltage. The drain voltage is applied to a gate electrode of a second field effect transistor that applies a data ramp voltage to the pixels. The pulse signal provides a small amount of drive in the second transistor.

US Patent:

53329970, Jul 26, 1994

Filed:

Sep 23, 1993

Appl. No.:

8/124679

Inventors:

Andrew G. F. Dingwall - Princeton NJ
Sherman Weisbrod - Skillman NJ

Assignee:

RCA Thomson Licensing Corporation - Princeton NJ

International Classification:

H03M 166

US Classification:

341150

Abstract:

A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node. Following the data transfer onto the binary weighted capacitors, the switching transistors are precharged and, concurrently the N capacitors are connected in parallel to produce an analog voltage corresponding to the serial data.

US Patent:

54348994, Jul 18, 1995

Filed:

Aug 12, 1994

Appl. No.:

8/288793

Inventors:

Ruquiya I. A. Huq - Plainsboro NJ
Sherman Weisbrod - Skillman NJ

Assignee:

Thomson Consumer Electronics, S.A.

International Classification:

G11C 1928

US Classification:

377 78

Abstract:

A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remain high for most of the vertical interval.

US Patent:

56003455, Feb 4, 1997

Filed:

Mar 6, 1995

Appl. No.:

8/398822

Inventors:

Andrew G. F. Dingwall - Princeton NJ
Sherman Weisbrod - Skillman NJ

Assignee:

Thomson Consumer Electronics, S.A. - Courbevoie

International Classification:

G02F 1133
G09G 336

US Classification:

345100

Abstract:

A liquid crystal display includes pixels that are arranged in columns and rows. Data line drivers responsive to a video signal develop output signals in data lines that correspond with the columns, respectively. An adjustment data line driver is provided. The adjustment data line driver is responsive to a reference DC constant signal at a mid-range of the video signal. An output signal of the adjustment data line driver is coupled to the other data line drivers in a negative feedback manner to compensate for output signal variations in the other data line drivers.

US Patent:

41830628, Jan 8, 1980

Filed:

Aug 7, 1978

Appl. No.:

5/931745

Inventors:

Sherman Weisbrod - Somerville NJ

Assignee:

RCA Corporation - New York NY

International Classification:

H04N 566
H04N 312
H05B 3700
G09F 900

US Classification:

358230

Abstract:

A horizontal sync signal simultaneously addresses a second counter and a first memory addressing circuit comprising a frequency multiplier connected to a first counter. The output of the first counter addresses the first memory. A comparator compares the outputs from the first memory and the second counter, and generates an output which may be compensated if necessary to subsequently assure proper sequencing of the display device. The comparator output addresses a second memory. Outputs from the second memory and the second counter are combined in an adder and the summation thereof are fed into a subtractor along with the output of the first memory. The output of the subtractor is fed into a binary-to-decimal converter which in turn feeds a row electrode driver circuit.