Sheldon Bernard Levenstein

US Patent:

6567839, May 20, 2003

Filed:

Oct 23, 1997

Appl. No.:

08/957002

Inventors:

John Michael Borkenhagen - Rochester MN
Richard James Eickemeyer - Rochester MN
William Thomas Flynn - Rochester MN
Sheldon Bernard Levenstein - Rochester MN
Andrew Henry Wottreng - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

709103, 709107, 709108, 712 23, 712205

Abstract:

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor.

US Patent:

6557084, Apr 29, 2003

Filed:

Jul 13, 1999

Appl. No.:

09/351654

Inventors:

Donald Lee Freerksen - Rochester MN
Sheldon Bernard Levenstein - Austin TX
Gary Michael Lippert - Kasson MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711147, 711150, 711151, 711152, 711158, 710 28, 710 40, 710244

Abstract:

According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locations. In particular, load-invalidate-load sequences are changed to loadâload sequences with the current invention. Furthermore, contention for a shared memory location will be reduced in particular situations when using the current invention.

US Patent:

7092270, Aug 15, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/880719

Inventors:

Michael Ju Hyeok Lee - Austin TX, US
Sheldon B. Levenstein - Austin TX, US
Edelmar Seewann - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 15/00

US Classification:

365 49, 365190

Abstract:

An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e. g. , more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.

US Patent:

7197604, Mar 27, 2007

Filed:

Oct 14, 2004

Appl. No.:

10/965151

Inventors:

Guy Lynn Guthrie - Austin TX, US
Sheldon B. Levenstein - Austin TX, US
William John Starke - Round Rock TX, US
Derek Edward Williams - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711142, 711125, 711141, 711144, 711145, 711156, 712216, 712234

Abstract:

A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

US Patent:

7200717, Apr 3, 2007

Filed:

Oct 14, 2004

Appl. No.:

10/965144

Inventors:

Guy Lynn Guthrie - Austin TX, US
Sheldon B. Levenstein - Austin TX, US
William John Starke - Round Rock TX, US
Derek Edward Williams - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711125, 711141, 711142, 711145, 711156, 712216, 712234

Abstract:

A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

US Patent:

7228385, Jun 5, 2007

Filed:

Oct 14, 2004

Appl. No.:

10/965113

Inventors:

Guy Lynn Guthrie - Austin TX, US
Sheldon B. Levenstein - Austin TX, US
William John Starke - Round Rock TX, US
Derek Edward Williams - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711118, 711123, 711125, 711133, 711136, 711142, 711143

Abstract:

A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

US Patent:

7284094, Oct 16, 2007

Filed:

Feb 9, 2005

Appl. No.:

11/054293

Inventors:

David Allen Hrusecky - Cedar Park TX, US
Sheldon B. Levenstein - Austin TX, US
Bruce Joseph Ronchetti - Austin TX, US
Anthony Saporito - Hyde Park NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711128

Abstract:

A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.

US Patent:

7302525, Nov 27, 2007

Filed:

Feb 11, 2005

Appl. No.:

11/055828

Inventors:

Eric Jason Fluhr - Round Rock TX, US
Sheldon B. Levenstein - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02

US Classification:

711118, 711201

Abstract:

A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.