Shankar Ganapathysubramanian

US Patent:

7719109, May 18, 2010

Filed:

Sep 29, 2006

Appl. No.:

11/541233

Inventors:

Mitul Modi - Phoenix AZ, US
Sudarshan V. Rangaraj - Chandler AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US
Richard J. Harries - Chandler AZ, US
Sankara J. Subramanian - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/10
H01L 23/34

US Classification:

257706, 257702, 257703, 257712, 257E2308

Abstract:

A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

US Patent:

7759780, Jul 20, 2010

Filed:

Sep 30, 2008

Appl. No.:

12/242398

Inventors:

Nirupama Chakrapani - Gilbert AZ, US
Vijay S Wakharkar - Paradise Valley AZ, US
Janet Feng - Chandler AZ, US
Nisha Ananthakrishnan - Chandler AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US
Gregory S Constable - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/29

US Classification:

257678, 257787

Abstract:

A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

US Patent:

8186051, May 29, 2012

Filed:

Mar 28, 2008

Appl. No.:

12/079785

Inventors:

Aleksandar Aleksov - Chandler AZ, US
Vladimir Noveski - Chandler AZ, US
Sujit Sharan - Chandler AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara

International Classification:

H05K 3/02

US Classification:

29847, 29830, 29846, 29852

Abstract:

Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.

US Patent:

8304065, Nov 6, 2012

Filed:

Dec 28, 2009

Appl. No.:

12/655282

Inventors:

Leonel Arana - Phoenix AZ, US
Dingying Xu - Maricopa AZ, US
Vijay Wakharkar - Paradise Valley AZ, US
Wen Feng - Chandler AZ, US
Nirupama Chakrapani - Gilbert AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US
Jorge Sanchez - Chandler AZ, US
Mohit Mamodia - Chandler AZ, US

International Classification:

B32B 7/02

US Classification:

428220, 428212, 428323, 428352, 428113, 428121, 428464

Abstract:

A treatment for a microelectronic device comprises a dicing tape () and a polymer composite film () having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50 Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

US Patent:

8604353, Dec 10, 2013

Filed:

Jan 19, 2012

Appl. No.:

13/374858

Inventors:

Aleksandar Aleksov - Chandler AZ, US
Vladimir Noveski - Chandler AZ, US
Sujit Sharan - Chandler AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 1/03
B23K 1/20
B23K 31/02
B05D 5/12
B05D 3/00

US Classification:

174258, 427123, 228203

Abstract:

A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

US Patent:

20080001282, Jan 3, 2008

Filed:

Jun 30, 2006

Appl. No.:

11/479258

Inventors:

Mitul Modi - Phoenix AZ, US
Sudarshan V. Rangaraj - Chandler AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US
Richard J. Harries - Chandler AZ, US
Sankara J. Subramanian - Chandler AZ, US

International Classification:

H01L 23/10

US Classification:

257710

Abstract:

A microelectronic assembly is provided, comprising at least a first microelectronic die carrying a microelectronic circuit, at least a first periphery seal attached to an edge of a surface of the microelectronic die, at least a first solder thermal interface material attached to a central region of the surface of the microelectronic die, the solder thermal interface material having a higher thermal conductivity than the periphery seal, and a thermally conductive member attached to the periphery seal and the solder thermal interface material on a side thereof opposing the microelectronic die.

US Patent:

20080079129, Apr 3, 2008

Filed:

Sep 29, 2006

Appl. No.:

11/540045

Inventors:

Shankar Ganapathysubramanian - Phoenix AZ, US
Sandeep Sane - Chandler AZ, US

International Classification:

H01L 21/00

US Classification:

257678, 438106

Abstract:

Semiconductor packages and methods to fabricate thereof are described. A decoupling assembly is disposed between a package substrate and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is de-coupled from a socket and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is decoupled from a substrate. A decoupling assembly includes a clamping device, springs, and shape memory alloy rods. The shape memory alloy rods are actuators that generate motion or a pre-programmed shape to apply force when thermally excited. When the thermal excitation or other stimulus is removed, the shape memory alloy rods tend to return to their original shape, thus relieving any load or motion generated.

US Patent:

20080137318, Jun 12, 2008

Filed:

Dec 8, 2006

Appl. No.:

11/636250

Inventors:

Sudarshan Rangaraj - Chandler AZ, US
Shankar Ganapathysubramanian - Phoenix AZ, US
Richard Harries - Chandler AZ, US
Mitul Modi - Phoenix AZ, US
Sankara J. Subramanian - Chandler AZ, US

International Classification:

H05K 7/02
H05K 3/22

US Classification:

361807, 29848

Abstract:

A compliant structure for an electronic device comprises a substrate () composed of a first material () and a compliant zone () within the substrate. A plurality of solder joints () are located between, and form a connection between, the substrate and the electronic device (). The compliant zone reduces the degree of deformation experienced by the solder joints due to thermal mismatch loading between the substrate and the die during attachment of the die to the substrate (chip attach). This reduction in solder joint deformation reduces the likelihood that the solder joints will crack.