Shane C Hollmer

US Patent:

6373742, Apr 16, 2002

Filed:

Oct 12, 2000

Appl. No.:

09/689036

Inventors:

Kazuhiro Kurihara - Sunnyvale CA
Shane C. Hollmer - San Jose CA

Assignee:

Advanced Micro Device, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 506

US Classification:

365 63, 365 51, 36523006, 36518908

Abstract:

A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

US Patent:

6381163, Apr 30, 2002

Filed:

Jun 4, 2001

Appl. No.:

09/873927

Inventors:

Kazuhiro Kurihara - Sunnyvale CA
Shane Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1500

US Classification:

365 49, 36518911

Abstract:

A memory device with a CAM cell and a read circuit are disclosed for reading a CAM cell using a boosted CAM gate voltage. The CAM read circuit comprises a voltage booster connected between the gate terminal of the CAM cell and a supply voltage, which provides a boosted voltage to the gate terminal of the CAM cell during a CAM read operation. Also disclosed is a method for reading a memory device CAM cell, wherein a boosted voltage is provided to the CAM cell gate.

US Patent:

6411069, Jun 25, 2002

Filed:

Aug 31, 1999

Appl. No.:

09/387018

Inventors:

Shane C. Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G05F 140

US Classification:

323283, 323288, 363 60

Abstract:

A refresh mechanism refreshes a supplied capacitor of a capacitor divider circuit at an interval that keeps an amount of charge degradation at a coupled up capacitor to less than a predetermined threshold. A node between the supplied capacitor and the coupled up capacitor provides a voltage sampling node having a divided voltage. Timing for the refresh operations may be established via internal clocks or internal oscillators running at multiples of other circuits already internal to the device utilizing the divided voltage. The divided voltage is then utilized for comparison, feedback (voltage regulation, for example), or other purposes. The invention is applicable to all types of circuits where degradation occurs due any type of leakage or other permutations affecting circuit operations.

US Patent:

6418054, Jul 9, 2002

Filed:

Aug 31, 1999

Appl. No.:

09/387421

Inventors:

Shane C. Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

3651852, 36518524, 365210

Abstract:

Programming lines are attached to reference cells of a memory device. A state machine controls voltages and/or currents applied to the reference cells via the programming lines to program and verify a program state of the reference cells. The state machine utilizes existing array cell programming operations conducted by the programming lines to the reference cells. The utilization of internal circuitry of the memory device in the programming of reference cells reduces the sort and test time of the memory device. The memory device may be a flash memory device or any device having reference cells, and the reference cells may be of any configuration or structure, including nitride layer cells.

US Patent:

6472898, Oct 29, 2002

Filed:

Nov 22, 2000

Appl. No.:

09/718986

Inventors:

Shane Hollmer - San Jose CA
Santosh Yachareni - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3126

US Classification:

324765, 3241581

Abstract:

A method and system for testing a semiconductor memory device applies defined test voltages to a semiconductor memory device in a manner that minimizes a time lapse during shifting from one voltage level to another or one voltage range to another. The system includes registers for storing codewords. Each codeword represents a discrete voltage level. The registers have inputs and outputs. Digital-to-analog converters are coupled to the outputs of the registers for converting a codeword into a corresponding analog voltage with a discrete voltage level. A multiplexer derives a test output voltage from the analog voltage, an external voltage, or both. A mode controller controls the multiplexer to derive the test output voltage. The test output voltage is compliant with defined voltage ranges associated with corresponding modes.

US Patent:

6477083, Nov 5, 2002

Filed:

Oct 11, 2000

Appl. No.:

09/686685

Inventors:

Richard M. Fastow - Cupertino CA
Mark W. Randolph - San Jose CA
Shane C. Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518516, 36518505, 365103

Abstract:

A bit line selector for a virtual ground non-volatile read only memory (âNROMâ) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.

US Patent:

6504757, Jan 7, 2003

Filed:

Aug 3, 2001

Appl. No.:

09/922415

Inventors:

Shane C. Hollmer - San Jose CA
Quang Binh - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518518, 36518517

Abstract:

A method for boosting potential in the channel of unselected memory cells on a selected bit-line. In this method, a first voltage is applied to all the word-lines of the memory cells in the string. A second voltage is then applied to word-lines adjacent the selected word lines to isolate the selected memory cell. Next, a programming voltage is applied to the selected word-line. In one embodiment, a time delay is applied between applying the second voltage and applying the third voltages to ensure isolation of the selected memory cell before applying the third voltage.

US Patent:

6510082, Jan 21, 2003

Filed:

Oct 23, 2001

Appl. No.:

09/999869

Inventors:

Binh Q. Le - San Jose CA
Michael A. Van Buskirk - Saratoga CA
Santosh K. Yachareni - Santa Clara CA
Michael S. C. Chung - San Jose CA
Kazuhiro Kurihara - Sunnyvale CA
Shane Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518516, 36518521

Abstract:

A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e. g. , about 1. 2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e. g. , about 1. 2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.