Shalin U Sheth

US Patent:

7550324, Jun 23, 2009

Filed:

Nov 15, 2007

Appl. No.:

11/985501

Inventors:

Steven E. McNeil - Rio Rancho NM, US
Shalin Umesh Sheth - San Francisco CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173
H03K 19/177
H01L 25/00
G06F 17/50

US Classification:

438132, 326 37, 326 38, 326 39, 326 40, 326 41, 326 47, 326101, 716 16, 716 19, 716 20, 716 21

Abstract:

A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

US Patent:

7987358, Jul 26, 2011

Filed:

Jun 9, 2006

Appl. No.:

11/450756

Inventors:

Steven K. Knapp - Soquel CA, US
Shalin Umesh Sheth - San Francisco CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 29/06

US Classification:

713160, 713168, 713189, 713190, 713191, 713192, 713193, 726 2, 380 44, 380278

Abstract:

Methods of authenticating a user design in a programmable integrated circuit. The methods utilize an identifier unique to the programmable IC and a data word taken from the user design. The data word can be unique to the design and can include a string of data taken from the configuration data for the design, or the values of circuit nodes read from selected points throughout the design. A function is performed on the identifier and the data word, producing a key specific to the user design as implemented in that programmable IC. The key is compared to an expected value. When the key matches the expected value, the user design is enabled. When the key does not match the expected value, at least a portion of the user design is disabled. Circuitry for performing the steps of the method can be implemented in the programmable resources of the programmable IC.

US Patent:

7339400, Mar 4, 2008

Filed:

Jun 9, 2006

Appl. No.:

11/449935

Inventors:

Steven E. McNeil - Rio Rancho NM, US
Shalin Umesh Sheth - San Francisco CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173
H03K 19/177
H03K 19/00

US Classification:

326 41, 326 38, 326 39, 326 40, 326 47, 326101

Abstract:

A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.