Sergey V Gribok

US Patent:

7308633, Dec 11, 2007

Filed:

Nov 30, 2004

Appl. No.:

10/999720

Inventors:

Alexandre Andreev - San Jose CA, US
Sergey Gribok - Santa Clara CA, US
Anatoli Bolotov - Cupertino CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 31/28
G11C 29/00

US Classification:

714733, 714718

Abstract:

A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.

US Patent:

7328382, Feb 5, 2008

Filed:

Nov 9, 2005

Appl. No.:

11/270077

Inventors:

Alexander E. Andreev - San Jose CA, US
Sergey V. Gribok - Santa Clara CA, US
Anatoli A. Bolotov - Cupertino CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714718, 714733

Abstract:

The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller.

US Patent:

7430694, Sep 30, 2008

Filed:

Jan 20, 2005

Appl. No.:

11/038698

Inventors:

Alexander E. Andreev - San Jose CA, US
Sergey V. Gribok - Santa Clara CA, US
Anatoli A. Bolotov - Cupertino CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G11C 29/00
G06F 12/00

US Classification:

714718, 711202

Abstract:

The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2,. . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f f,. . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r, r,. . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R.

US Patent:

7493519, Feb 17, 2009

Filed:

Oct 24, 2005

Appl. No.:

11/257470

Inventors:

Alexander E. Andreev - San Jose CA, US
Vojislav Vukovic - Santa Clara CA, US
Sergey Gribok - Santa Clara CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 11/00

US Classification:

714 29

Abstract:

A method for verifying the functionality of a repair system of configurable memory that functions to replace memory that fails predetermined tests with unused memory that passes the tests. The method includes the steps of providing a matrix comprising a plurality of reconfigurable memory blocks, providing an emulation system, generating a substitute memory block for each of the reconfigurable memory blocks utilizing the emulation system computing platform, providing a memory design that incorporates the substitute memory blocks, generating files for mapping errors into the reconfigurable memory blocks and providing a control file associated with the emulation system, and operating the emulation system to emulate the memory design.

US Patent:

7546505, Jun 9, 2009

Filed:

Nov 8, 2006

Appl. No.:

11/557513

Inventors:

Sergey Gribok - Santa Clara CA, US
Alexander Andreev - San Jose CA, US
Ivan Pavisic - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 31/28
G11C 29/00

US Classification:

714733, 714718, 714734

Abstract:

A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.

US Patent:

7656340, Feb 2, 2010

Filed:

Jun 6, 2008

Appl. No.:

12/134523

Inventors:

Sergey Gribok - San Jose CA, US
Choshu Ito - San Mateo CA, US
William Loh - Fremont CA, US
Erik Chmelar - Midland MI, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03M 1/38

US Classification:

341161, 341155

Abstract:

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.

US Patent:

7913149, Mar 22, 2011

Filed:

Dec 20, 2006

Appl. No.:

11/613256

Inventors:

Sergey Gribok - Santa Clara CA, US
Alexander Andreev - San Jose CA, US
Igor Vikhliantsev - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03M 13/00

US Classification:

714781, 714755

Abstract:

A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form.

US Patent:

7934139, Apr 26, 2011

Filed:

Dec 1, 2006

Appl. No.:

11/565670

Inventors:

Alexander Andreev - San Jose CA, US
Igor Vikhliantsev - San Jose CA, US
Sergey Gribok - Santa Clara CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03M 13/00

US Classification:

714752

Abstract:

An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.