Reshmi Mitra - South Portland ME, US Scott Ruby - Lisbon Falls ME, US Sergai Drizlikh - Scarborough ME, US Thomas Francis - South Portland ME, US Robert Tracy - South Portland ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/8238 H01L 23/62
US Classification:
438210, 438329, 438382, 438751, 257363, 257380
Abstract:
An electrical resistance is produced in a semiconductor device by first providing a semiconductor resistor structure that includes a semiconductor resistor having formed thereon a native oxide layer. A portion of the native oxide layer that overlies a corresponding top surface portion of the semiconductor resistor is removed, in order to expose the top surface portion of the semiconductor resistor. Metal is deposited on the exposed top surface portion of the semiconductor resistor. A chemical reaction is effectuated in order to reduce the likelihood of metal reacting with the underlying silicon on any portion of the semiconductor resistor other than the top surface portion thereof. The chemical reaction can be an oxidation reaction that produces on the semiconductor resistor structure an oxide layer other than the native oxide layer and substantially thicker than the native oxide layer.
System And Method For Manufacturing An Emitter Structure In A Complementary Bipolar Cmos Transistor Manufacturing Process
Todd Patrick Thibeault - Gorham ME, US Steven J. Adler - Cape Elizabeth ME, US Scott David Ruby - Durham ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438343, 438309
Abstract:
A system and method are disclosed for manufacturing an emitter structure in a complementary bipolar complementary metal oxide semiconductor (CBiCMOS) transistor manufacturing process. A protective layer is formed over an emitter layer in a transistor structure and lateral portions of the protective layer and the emitter layer are etched to form an emitter structure. An oxide layer is then deposited over the transistor structure and an etchback process is performed to remove portions of the oxide layer from the top of the protective layer. A source/drain implant process is then performed to implant an extrinsic base region of the transistor. The protective layer protects the emitter structure from the implant process. Then the protective layer is removed from the emitter structure.