Scarlett Zhijia Wu

US Patent:

6473558, Oct 29, 2002

Filed:

Jun 26, 1998

Appl. No.:

09/105938

Inventors:

Scarlett Wu - Hillsborough CA
Arvind Patwardhan - San Jose CA
Osamu Takiguchi - Tokyo, JP

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04N 5783

US Classification:

386 68, 386125, 386126

Abstract:

A method and system for displaying a series of video frames in reverse order. The video frames are received in groups of pictures (GOPs) from a storage medium. The method comprises steps of (a) decoding and storing a number of frames from an initial GOP into frame buffers according to an ordering of the frame buffers, (b) displaying the stored frames according to the reverse ordering of the frame buffers, (c) decoding and storing a number of frames from a first preceding GOP according to the reverse ordering of the frame buffers, (d) displaying the stored frames according to the ordering of the frame buffers, (e) decoding and storing a number of frames from a second preceding GOP according to the ordering of the frame buffers, and (f) repeating steps (b)-(e),for prior first and second preceding GOPs.

US Patent:

6513126, Jan 28, 2003

Filed:

Jan 6, 2000

Appl. No.:

09/477692

Inventors:

Wen Huang - Sunnyvale CA
Scarlett Wu - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 104

US Classification:

713500, 713501, 713502, 713503, 713600

Abstract:

An interface is provided between a digital signal processor or the like and an output encoder or the like that is capable of counting a system clock of the digital signal processor, generally having a higher clock rate, with respect to at least one or more clocks generally having a lower clock rate. The digital signal processor system clock is passed to the interface that has at least one or more counters. When the accumulation of the system clock reaches a corresponding number of the other clocks, a domain module in the output encoder is triggered, and the corresponding clock counters are reset. The interface may be implemented as a software modeling routine suitable for utilization by a digital signal processor simulator to facilitate complete whole cycle simulation in which multiple clocks having various clock rates may be simulated and compared with a behavior reference. The interface provides cycle-by-cycle comparison of the clocks in an asynchronous domain. The output encoder may be compliant with an International Elector-technical Commission standard such as an audio encoder standard.

US Patent:

6557117, Apr 29, 2003

Filed:

Jun 22, 1999

Appl. No.:

09/337953

Inventors:

Scarlett Wu - Hillsborough CA
Darren Neuman - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04B 174

US Classification:

714 30, 714700, 714733, 375226, 375376, 324 7648, 324 7653

Abstract:

An on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus generally comprises a finite state machine and testing circuitry. The finite state machine may be for (i) receiving the reference clock signal and for (ii) producing testing signals for the phase locked loop module. The testing circuitry may be coupled to the finite state machine for (i) receiving the output clock signal, (ii) determining whether the characteristics of the output clock signal meet a predetermined criteria for open and close loop phase locked loop module operation, and (iii) outputting a test signal that indicates proper phase locked loop module operation if the characteristics of the output clock signal meet the predetermined criteria.

US Patent:

6704846, Mar 9, 2004

Filed:

Jun 26, 1998

Appl. No.:

09/105492

Inventors:

Scarlett Z. Wu - Hillsborough CA
Darren D. Neuman - San Jose CA
Arvind B. Patwardhan - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1200

US Classification:

711150

Abstract:

A video decoding system includes an embedded microcontroller that provides memory arbitration in addition to processing and control functions. The microcontroller architecture provides a first-in, first-out (FIFO) queue for storing memory access instructions and a processing logic for executing software instructions. The microcontroller processing logic determines which components within the decoding system need access to memory and stores a sequence of memory access instructions into the FIFO queue. Each memory access instruction is associated with one decoder component. When main memory becomes available, a memory access instruction is dequeued from the FIFO and transmitted to the associated decoder component, which is then permitted to access memory. The microcontroller receives indicator signals from the decoder components that indicate when the decoder components have finished accessing memory and, thus, when the memory device is available for subsequent transactions.

US Patent:

61608475, Dec 12, 2000

Filed:

Jun 26, 1998

Appl. No.:

9/106049

Inventors:

Scarlett Wu - Hillsborough CA
Arvind Patwardhan - San Jose CA
Youichi Obana - Tokyo, JP

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04N 712
H04N 1102
H04N 1104

US Classification:

3752401

Abstract:

A method and system for displaying a series of video frames so that picture corruption from video channel underflows is avoided. The method comprises the steps of receiving a data stream with compressed video data for the series of video frames, storing the compressed video data in a channel buffer, processing a video frame if sufficient compressed video data for the video frame is stored in the channel buffer, and displaying a preceding video frame if insufficient compressed video data for the video frame is stored in the channel buffer. The system, which displays a series of video frames, also addresses the issue of video channel underflow. The video frames are received as compressed video data in a data stream that also includes size parameters, such as the vbv. sub. -- delay parameter in the frame headers of MPEG frames, for each video frame in the series of video frames. The system comprises an input for receiving a data stream, a channel buffer for storing the compressed video data, a decoder that decodes the compressed video data and provides the decoded video data to a display device, and an underflow detector that compares the amount of compressed video data in the channel buffer to the required amount of compressed video data.

US Patent:

61184918, Sep 12, 2000

Filed:

Feb 20, 1997

Appl. No.:

8/803504

Inventors:

Scarlett Wu - Hillsborough CA
Darren D Neuman - San Jose CA
Robert F Bishop - Morgan Hill CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04N 508

US Classification:

348526

Abstract:

A system and method for synchronizing a decoded, interlaced-field data stream with an interlaced field display. A system for displaying an MPEG encoded data stream includes an MPEG decoder which converts the encoded data stream into a sequence of frames. Each frame has an associated top field, bottom field, top-field-first flag, and repeat-first-field flag. The system also includes a display processor which receives the flags and determines a field display sequence for each frame which conforms to an overall display sequence which strictly alternates between top and bottom fields. This strict alternation in enforced even when the decoded field sequence does not adhere to a strict alternation. The system achieves this result with a worst-case temporal distortion of one field by inserting or omitting a 3:2 pulldown frame at each broken alternation point.