Sandra S Woodward

Author:

Sandra Kytle Woodward

ISBN #:

0898651646

US Patent:

6791352, Sep 14, 2004

Filed:

Feb 8, 2002

Appl. No.:

10/072103

Inventors:

David Joel Verdoorn - Byron MN
Sandra S. Woodward - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19173

US Classification:

326 38, 326 16, 326 47, 327407

Abstract:

In a first aspect, an apparatus is provided that is adapted to multiplex debug signals of an integrated circuit. The apparatus includes at least a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is adapted to receive first debug signals from the integrated circuit and to selectively multiplex at least a first portion of the first debug signals onto a first bus. The second multiplexing circuit is adapted to receive second debug signals from the integrated circuit and to selectively multiplex at least a first portion of the second debug signals onto a second bus. The apparatus further includes a logic circuit adapted to combine any debug signals of the first and second buses onto a third bus. An output stage of the apparatus is adapted to selectively output debug signals of the third bus. Numerous other aspects are provided, as are systems and methods.

US Patent:

7305524, Dec 4, 2007

Filed:

Oct 8, 2004

Appl. No.:

10/961749

Inventors:

Russell D. Hoover - Rochester MN, US
Eric O. Mejdrich - Rochester MN, US
Jon K. Kriegel - Rochester MN, US
Sandra S. Woodward - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133, 711143, 711146, 711144, 345502

Abstract:

Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

US Patent:

7355601, Apr 8, 2008

Filed:

Dec 16, 2005

Appl. No.:

11/303525

Inventors:

Jeffrey A. Andrews - Sunnyvale CA, US
Nicholas R. Baker - Cupertino CA, US
J. Andrew Goossen - Issaquah WA, US
Russell D. Hoover - Rochester MN, US
Eric O. Mejdrich - Rochester MN, US
Sandra S. Woodward - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY
Microsoft Corporation - Redmond WA

International Classification:

G06F 12/08
G06F 9/46
G06F 13/20
G06F 15/80
G06F 13/28
G09G 9/36
G06T 15/00
G06F 15/16
G06F 15/78

US Classification:

345505, 345502, 345557, 345543, 345574, 711 3, 711118, 711125, 711143, 712 10, 712 34, 382233

Abstract:

A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

US Patent:

7475190, Jan 6, 2009

Filed:

Oct 8, 2004

Appl. No.:

10/961752

Inventors:

Russell D. Hoover - Rochester MN, US
Eric O. Mejdrich - Rochester MN, US
Sandra S. Woodward - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/167
G06F 12/00

US Classification:

711118, 709216, 709213, 711145, 711128, 711153, 711129, 711113

Abstract:

Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.

US Patent:

7577794, Aug 18, 2009

Filed:

Oct 8, 2004

Appl. No.:

10/961751

Inventors:

Bruce L. Beukema - Hayfield MN, US
Russell D. Hoover - Rochester MN, US
Jon K. Kriegel - Rochester MN, US
Eric O. Mejdrich - Rochester MN, US
Sandra S. Woodward - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711146, 711133

Abstract:

Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.

US Patent:

20060080511, Apr 13, 2006

Filed:

Oct 8, 2004

Appl. No.:

10/961742

Inventors:

Russell Hoover - Rochester MN, US
Jon Kriegel - Rochester MN, US
Eric Mejdrich - Rochester MN, US
Sandra Woodward - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141000, 711146000

Abstract:

Methods and apparatus are provided that may be utilized to maintain a copy of a processor cache directory on a remote device that may access data residing in a cache of the processor. Enhanced bus transactions containing cache coherency information used to maintain the remote cache directory may be automatically generated when the processor allocates or de-allocates cache lines. Rather than query the processor cache directory prior to each memory access to determine if the processor cache contains an updated copy of requested data, the remote device may query its remote copy.

US Patent:

20060095672, May 4, 2006

Filed:

Feb 25, 2005

Appl. No.:

11/065343

Inventors:

Jeffrey Andrews - Sunnyvale CA, US
Nicholas Baker - Cupertino CA, US
J. Goossen - Issaquah WA, US
Michael Abrash - Kirkland WA, US
Russell Hoover - Rochester MN, US
Eric Mejdrich - Rochester MN, US
Sandra Woodward - Rochester MN, US

International Classification:

G06F 12/14

US Classification:

711118000

Abstract:

A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data

US Patent:

20070294481, Dec 20, 2007

Filed:

Aug 31, 2007

Appl. No.:

11/848960

Inventors:

Russell Hoover - Rochester MN, US
Eric Mejdrich - Rochester MN, US
Jon Kriegel - Rochester MN, US
Sandra Woodward - Rochester MN, US

International Classification:

G06F 12/00

US Classification:

711133000

Abstract:

Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.