San L Lin

US Patent:

20050235089, Oct 20, 2005

Filed:

Mar 29, 2005

Appl. No.:

11/091423

Inventors:

Fred Cheng - Hsinchu, TW
Chen-Min Chiang - Hsinchu, TW
Jenn-Shiang Lai - Chung Li City, TW
San Lin - Fremont CA, US
Jingyu Hu - Fremont CA, US
Aung Oo - Fremont CA, US
Zhihui Luo - Fremont CA, US

International Classification:

G06F013/00

US Classification:

710305000

Abstract:

The present invention relates to a method and apparatus universal serial bus (USB) physical layer. An UTM interface control logic receives a transmit data packet of USB 2.0 transceiver macrocell interface (UTMI). A transmit first-in first-out (FIFO) unit receives the transmit data packet output from the UTM interface control logic. A transmit unit receives the transmit data packet output from the transmit FIFO. An analog front-end (AFE) receives the transmitted data packet output of the transmit unit. A receive unit receives a receive data packet output from the AFE. A receive FIFO receives the receive data packet output from the receive unit and connected to the UTM interface control logic, whereby the receive data packet is output to the USB 2.0 transceiver macrocell interface.

US Patent:

53672488, Nov 22, 1994

Filed:

Oct 13, 1992

Appl. No.:

7/960514

Inventors:

San L. Lin - San Jose CA

Assignee:

Winbond Electronics North America Corporation - San Jose CA

International Classification:

G05F 320
H03K 301

US Classification:

323312

Abstract:

The invention provides a method and apparatus for precise modulation of a reference current. A current generating apparatus in accordance with the invention is provided on an integrated circuit chip and includes a series connected chain comprising in the recited order: (a) an externally-set reference current source; (b) a current-to-voltage (I/V) converter for converting the reference current into an on-chip reference voltage, V. sub. ref ; (c) a voltage-to-current (V/I) converter for converting the reference voltage V. sub. ref into an on-chip, internal reference current I. sub. iref ; (d) a single-ended, voltage-operated current switch for modulating the internal reference current I. sub. iref to produce therefrom a modulated current signal, I. sub. M ; (e) a current-driven filter which receives the modulated current signal I. sub.

US Patent:

53862074, Jan 31, 1995

Filed:

Jun 23, 1992

Appl. No.:

7/902632

Inventors:

San L. Lin - San Jose CA

Assignee:

Winbond Electronics North America Corporation - San Jose CA

International Classification:

G06F 702

US Classification:

3401462

Abstract:

A comparator that may be used in data communications transmission lines, in particular, an Ethernet Twisted-Pair line. The comparator accepts as input the differential voltage from the transmission lines. The comparator uses feedback circuitry to monitor particular voltages within the comparator and adjust them as necessary to mitigate the effect of bias offset within the comparator that may result from, for instance, temperature driven device parameter variations. The comparator also minimizes the effect of power supply noise. The feedback circuitry ensures that as the comparator input differential voltage approaches zero (i. e. , when the comparator outputs should switch from a high voltage to a low voltage or vice versa), the input of a comparator output amplifier is situated in the middle of the high gain region of the output amplifier, ready to quickly trigger switching of the comparator output when the comparator input differential voltage crosses zero volts. In one embodiment, the feedback circuitry comprises an operational amplifier and two resistive-capacitive structures.

US Patent:

53629949, Nov 8, 1994

Filed:

Oct 13, 1992

Appl. No.:

7/959853

Inventors:

San L. Lin - San Jose CA

Assignee:

Winbond Electronics North America Corporation - San Jose CA

International Classification:

H03K 524

US Classification:

327 72

Abstract:

A hysteresis comparator is disclosed which utilizes an on-chip bias generator, and incorporates circuitry which renders the decision voltages V. sub. P and V. sub. N insensitive to semiconductor process variations, independent of any critical reference voltages, and proportional to absolute temperature. Current sources coupled to positive and negative bias voltages are utilized to generate precise voltages across resistors to set the magnitude of V. sub. P and V. sub. N, which magnitudes are set by the ratios of like components existing within the same integrated circuit. Hysteresis comparators with precise and repeatable decision voltages can be implemented while consuming a minimum amount of semiconductor area.

US Patent:

54246610, Jun 13, 1995

Filed:

Aug 12, 1993

Appl. No.:

8/106098

Inventors:

San L. Lin - San Jose CA
Hwa-Jyun Chen - Shinchu, TW

Assignee:

Winbond Electronics North America Corp. - San Jose CA

International Classification:

G01R 1900
H03L 700
H03K 519

US Classification:

327 18

Abstract:

A sensor circuit is disclosed for use with a clock circuit providing a periodic timing signal to a clock output, wherein a timing reference for the periodic timing signal is provided by a crystal connected between a crystal input and a crystal output of the clock circuit, or alternatively provided by an external periodic logic signal coupled to the crystal input. The sensor circuit provides a sensor output in a first state, thereby indicating the presence of an external periodic logic signal timing reference, in response to at least a given number of large-signal voltage transitions on the crystal input within a certain period of time, and otherwise provides a second state on the sensor output, typically to indicate the presence of a crystal timing reference. Also disclosed is a clock circuit including a sensor circuit, and further including means for disabling a feedback resistor necessary for crystal operation when the timing reference is determined to be provided by an external periodic logic signal.

US Patent:

20190252239, Aug 15, 2019

Filed:

Feb 15, 2019

Appl. No.:

16/277104

Inventors:

- Santa Clara CA, US
Gaurav Thareja - Santa Clara CA, US
San Kuei Lin - Cupertino CA, US
Ching-Mei Hsu - Mountain View CA, US
Nitin K. Ingle - San Jose CA, US
Ajay Bhatnagar - Mountain View CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/764
H01L 29/06
H01L 29/66
H01L 27/092
H01L 29/78
H01L 21/8238

Abstract:

Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.