Joel Zvi Apisdorf - Reston VA, US Sam Brandon Sandbote - Reston VA, US Michael Daniel Poole - Reston VA, US
Assignee:
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F013/00
US Classification:
712235, 712 22
Abstract:
A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to the first processing element. A second processing element, coupled to the forwarding storage element, transmits a second memory address to the forwarding storage element. The forwarding storage transmits the second memory address to the first processing element, and the first processing element compares the second memory address with the first memory address.
System And Method For Processing Overlapping Tasks In A Programmable Network Processor Environment
Jack Bonnell Dennis - Belmont MA, US Joel Zvi Apisdorf - Reston VA, US Sam Brandon Sandbote - Reston VA, US
Assignee:
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F009/46
US Classification:
718100, 718102
Abstract:
A system and method process data elements on multiple processing elements. A first processing element processes a task. A second processing element, coupled to the first processing element, is associated with a task. The first processing element sends a critical-section end signal to the second processing element while processing the task at the first processing element. The second processing element resumes the task in response to receiving the critical-section end signal.
Shifter For Alignment With Bit Formatter Gating Bits From Shifted Operand, Shifted Carry Operand And Most Significant Bit
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F 9/315
US Classification:
712300, 712224
Abstract:
An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post processor to transfer a shift carry operand stored in the register to the shift post processor, and coupled to the shifter to store the shifted operand after any transfer of the shift carry operand. The shift post processor is coupled to the shifter and the register to process the shifted operand to generate an output based on at least a control signal and a mask field. The shift post processor comprises a decoder to decode the offset parameter into the mask field, the mask field having a plurality of mask bits, each of the mask bits corresponding to a bit position of the shifted operand.
Jack B. Dennis - Belmont MA, US Sam B. Sandbote - Reston VA, US
Assignee:
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F 3/00 G06F 15/16
US Classification:
710 45, 712 21
Abstract:
One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.
Full/Selector Output From One Of Plural Flag Generation Count Outputs
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert the buffer “Full” flag. In turn, the full flag is used by the instruction fetch logic as an indication of when to stop fetching further instructions.
Adaptive Control Of Multiplexed Input Buffer Channels
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
H04B 7/204
US Classification:
370319, 370230, 370412, 370413, 370414, 370419
Abstract:
The present invention is a technique to select an input port. A database stores records of input ports for a plurality of communication channels. Each of the records includes a timestamp and a ready status. The timestamp indicates a most recent service time. A selector selects one of the input ports based on the timestamp and the ready status. A listener updates the records.
License Records
Sam Brandon Sandbote
Address:
Dallas, TX
License #:
0402036723 - Expired
Category:
Professional Engineer License
Issued Date:
Dec 19, 2002
Expiration Date:
Dec 31, 2010
Type:
Professional Engineer
Name / Title
Company / Classification
Phones & Addresses
Sam B Sandbote Governing, Governing Person
SAM B SANDBOTE, PLLC
3120 State St APT J, Dallas, TX 75204 2001 S Mo Pac Expy APT 1926, Austin, TX 78746
Multiple
Independent Consultant
Wave Computing Oct 2014 - Nov 2016
Distinguished Architect
Photonic Oct 2012 - Jun 2014
Many-Core Architect
Soft Machines Jun 2011 - Jul 2012
Arm System Architect and Microarchitect
Solar Power Technologies Feb 2009 - Dec 2010
Co-Founder
Education:
Southern Methodist University 2005
Doctorates, Doctor of Philosophy, Architecture, Philosophy
Southern Methodist University 1996 - 1998
Masters, Electrical Engineering
Southern Methodist University 1993 - 1998
Bachelors, Electrical Engineering, Applied Mathematics
Highland Park High School
Skills:
Computer Architecture System Architecture Microarchitecture Microprocessors Network Processors Digital Signal Processing Arm Rtl Design Simulations C++ Physical Design Compilers Operating Systems Systemc Java Perl Neural Networks Artificial Neural Networks Vhdl Digital Signal Processors Arm Architecture Application Specific Integrated Circuits Architecture Verilog System on A Chip Processors Systemverilog Semiconductors Deep Learning Machine Learning Firmware
Languages:
English German
Certifications:
License 91497
Digital Asic/Processor Microarchitect, System Architect
PhotonIC - San Francisco Bay Area since Oct 2012
Multiprocessor Architect
Soft Machines - Santa Clara, CA Jun 2011 - Jul 2012
Butterfly
Solar Power Technologies Inc Mar 2009 - Sep 2010
Co-founder and Digital+Firmware Lead
Integral Wave Technologies Sep 2008 - Oct 2008
Sr. Digital IC Designer
Southern Methodist University Aug 2005 - Sep 2008
Ph.D. Student
Education:
Southern Methodist University 1996 - 1998
M.S.E.E., Electrical Engineering (DSP)
Southern Methodist University 1993 - 1998
B.S.E.E., Electrical Engineering
Southern Methodist University 1993 - 1997
B.S., Applied Mathematics
Southern Methodist University 2005
Ph.D., Computer Architecture
Skills:
Simulations ARM RTL design Integrated Circuit Design C C++ Digital Signal Processing Computer Architecture Microarchitecture Operating Systems Physical Design Java Perl Neural Networks Artificial Neural Networks SystemC Network Processors Compilers
Honor & Awards:
Eta Kappa Nu, Upsilon Pi Epsilon, Golden Key
Certifications:
PE (Professional Engineer), State of Texas PE (Professional Engineer), State of Virginia