Sajol C Ghoshal

US Patent:

7206369, Apr 17, 2007

Filed:

Oct 12, 2001

Appl. No.:

09/977045

Inventors:

Randall L. Findley - Austin TX, US
Sajol C. Ghoshal - Austin TX, US
Gregory E. Beers - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03D 3/24

US Classification:

375373, 327149, 327158

Abstract:

A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

US Patent:

7368798, May 6, 2008

Filed:

Nov 18, 2005

Appl. No.:

11/282804

Inventors:

John R. Camagna - El Dorado Hills CA, US
Sajol Ghoshal - Austin TX, US

Assignee:

Akros Silicon Inc. - Folsom CA

International Classification:

H01L 29/00

US Classification:

257499, 37039552, 37039553, 370910, 379324, 379413, 379 9336, 455574

Abstract:

Embodiments of the present invention provide an integrated circuit (IC) having an integrated DC-DC power converter therein. This IC is operable to support the distribution of combined power and data signals in a network environment such as an Ethernet network according to protocols such as the power over Ethernet (PoE) protocol. The IC includes a DC-DC power converter, a power feed circuit, and a network physical layer (PHY) module, wherein the PHY module may contain fine line structures susceptible to damage when exposed to excessive voltages. To prevent or reduce the likelihood of damage to the PHY module from voltages supplied to the DC-DC power converter, a common substrate ground is shared between the IC components.

US Patent:

7500116, Mar 3, 2009

Filed:

Aug 23, 2005

Appl. No.:

11/209950

Inventors:

John R. Camagna - El Dorado Hills CA, US
Sajol Ghoshal - Austin TX, US

Assignee:

Akros Silicon Inc. - Folson CA

International Classification:

G06F 1/26

US Classification:

713300, 370318

Abstract:

The present invention provides a method to at least partially power an Ethernet device from a plurality of balanced network power signals received through a network connection. This involves attaching the network device to the network, wherein network signals are received and contain both power signals and/or data signals. These network signals may be passed through surge protection and power-conditioning circuitry wherein the output of these circuits may be provided to a power absorbing circuit. This power absorbing circuit may separate the communication signal and power signal from the network signal. The communication signal may be passed to a network physical layer while the power signal may be passed to a power distribution module. Additionally, because certain embodiments may provide multiple pairs of network power signals to the power absorbing circuit, the current or power associated with each power signal must be sensed and balanced. This may be done with an active control circuit.

US Patent:

7610422, Oct 27, 2009

Filed:

Jul 26, 2007

Appl. No.:

11/881205

Inventors:

David Bliss - Loomis CA, US
Sajol Ghoshal - El Dorado Hills CA, US

Assignee:

Akros Silicon Inc. - Folsom CA

International Classification:

G06F 13/00

US Classification:

710110, 710105

Abstract:

An interface between two or more integrated circuit devices employs isolation techniques to provide electrical isolation of a digital signal for transmission of the digital signal between a master device and one or more slave devices. Unidirectional isolator channels are utilized to transmit bidirectional digital signals, and a selection of an isolator channel operating in an intended direction is performed by direction control logic. Logic that monitors read and write transactions operates to determine a desired direction of the digital signal and accordingly directs the digital signal through an appropriate isolator channel.

US Patent:

7620825, Nov 17, 2009

Filed:

Aug 19, 2005

Appl. No.:

11/207601

Inventors:

John R. Camagna - El Dorado Hills CA, US
Sajol Ghoshal - Austin TX, US
Francois Crepin - Orangevale CA, US

Assignee:

Akros Silicon Inc. - Folsom CA

International Classification:

G06F 1/26

US Classification:

713300, 713340

Abstract:

Embodiments of the present invention provide a network device operable to receive a network signal that may include both power and data from a coupled network. This network device includes a network connector and an integrated circuit. The network connector physically couples the network device to the network. An optional protection circuit may provide surge protection or incoming network signals received by the network device through the network connector. An optional switching/rectifying circuit sees the output of the protection circuit and is operable to rectify a power signal when contained within the network signal. The integrated circuit further includes a power feed circuit conductively coupled to the protection circuit and the rectifying circuit. This power feed circuit is operable to separate and pass the received data signal to a network physical layer and separate and pass the received power signal to a power management module. The power management module electrically couples to the integrated circuit but is not necessarily part of the integrated circuit.

US Patent:

7685452, Mar 23, 2010

Filed:

Nov 23, 2005

Appl. No.:

11/287408

Inventors:

John R. Camagna - El Dorado Hills CA, US
Philip Crawley - Folsom CA, US
Sajol Ghoshal - Austin TX, US

Assignee:

Akros Silicon Inc. - Folsom CA

International Classification:

G06F 1/00
G06F 11/30

US Classification:

713340, 713300, 330291, 330297

Abstract:

Embodiments of the present invention provide a power feed circuit operable to supply an Ethernet power signal to a coupled Ethernet network. This power feed circuit includes a number of input nodes, differential transistor pairs, active control circuits and output nodes. The input nodes receive a first power signal such as that provided by an isolated 48 volt power supply. Each transistor of the differential transistor pairs couples to one input node. These differential transistor pairs produce a second power signal which may be supplied to the Ethernet network. The active control circuits sense the second power signal passed by each transistor and are operable to apply a feedback signal to the differential transistor pairs based on the sensed power signal. At least one twisted pair couples to each differential transistor pair's output node and is operable to pass the Ethernet power signal.

US Patent:

7701731, Apr 20, 2010

Filed:

Feb 13, 2007

Appl. No.:

11/674395

Inventors:

Timothy A. Dhuyvetter - Arnold CA, US
Sajol Ghoshal - El Dorado Hills CA, US

Assignee:

Akros Silicon Inc. - Folsom CA

International Classification:

H02M 3/335

US Classification:

363 16

Abstract:

A method for transmitting an information signal across an isolation barrier comprises receiving an input signal, preconditioning the input signal according to a modulation function, passing the preconditioned signal through the isolation barrier, and recovering the passed signal according to a demodulation function corresponding to the modulation function, the recovered signal being operative as a feedback signal.

US Patent:

7706112, Apr 27, 2010

Filed:

Dec 19, 2006

Appl. No.:

11/613156

Inventors:

Philip John Crawley - Sacramento CA, US
Sajol Ghoshal - El Dorado Hills CA, US

Assignee:

Akros Silicon Inc. - Folsom CA

International Classification:

H02H 3/22

US Classification:

361 56, 361111

Abstract:

An active clamp device electrically couples first and second nodes in respective first and second supply domains referenced to ground potentials that can be different. The active clamp device comprises first and second active devices controlled by signals respectively referenced to the first and second supply domains that create a short-circuit or low impedance connection between the first and second nodes in normal operation and drive impedance between the first and second nodes high in response to a transient event.