Saibal Mukhopadhyay

US Patent:

7319343, Jan 15, 2008

Filed:

Apr 5, 2005

Appl. No.:

11/099386

Inventors:

Swarup Bhunia - Midnapur, IN
Hamid Mahmoodi - West Lafayette IN, US
Arijit Raychowhury - Calcutta, IN
Saibal Mukhopadhyay - West Lafayette IN, US
Kaushik Roy - West Lafayette IN, US

Assignee:

Purdue Research Foundation - Purdue University - West Lafayette IN

International Classification:

H03K 19/173
G01R 31/28

US Classification:

326 38, 326 16, 714727

Abstract:

A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

US Patent:

7642864, Jan 5, 2010

Filed:

Jan 29, 2008

Appl. No.:

12/021459

Inventors:

Jae-Joon Kim - Austin TX, US
Pong-Fei Lu - Yorktown Heights NY, US
Saibal Mukhopadhyay - Atlanta GA, US
Rahul M. Rao - Elmsford NY, US
Shao-yi Wang - Fremont CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 23/00
G01R 27/00
G01R 27/28
H03B 5/24
H03K 3/03

US Classification:

331 44, 331 57, 324600, 324649

Abstract:

A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

US Patent:

7673195, Mar 2, 2010

Filed:

Oct 3, 2007

Appl. No.:

11/866502

Inventors:

Jae-Joon Kim - Austin TX, US
Saibal Mukhopadhyay - Atlanta GA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00
G11C 7/06

US Classification:

714721, 36518907, 365200

Abstract:

A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

US Patent:

8086917, Dec 27, 2011

Filed:

Aug 17, 2009

Appl. No.:

12/542187

Inventors:

Jae-Joon Kim - Austin TX, US
Saibal Mukhopadhyay - Atlanta GA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00
G11C 7/00

US Classification:

714718, 36518911

Abstract:

A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

US Patent:

8176444, May 8, 2012

Filed:

Apr 20, 2009

Appl. No.:

12/426475

Inventors:

Shayak Banerjee - Austin TX, US
Dureseti Chidambarrao - Weston CT, US
James A. Culp - Newburgh NY, US
Praveen Elakkumanan - Hartsdale NY, US
Saibal Mukhopadhyay - Atlanta GA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 51, 716 52, 716 53, 716 54, 716 55, 716 56

Abstract:

A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

US Patent:

8418087, Apr 9, 2013

Filed:

Feb 13, 2012

Appl. No.:

13/371537

Inventors:

Shayak Banerjee - Austin TX, US
Dureseti Chidambarrao - Weston CT, US
James A. Culp - Newburgh NY, US
Praveen Elakkumanan - Hopewell Junction NY, US
Saibal Mukhopadhyay - Atlanta GA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 51, 716 52, 716 53, 716 54, 716 55, 716 56

Abstract:

A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

US Patent:

20070171748, Jul 26, 2007

Filed:

Jan 23, 2006

Appl. No.:

11/337348

Inventors:

Saibal Mukhopadhyay - West Lafayette IN, US
Hamid Mahmoodi - San Francisco CA, US
Kaushik Roy - West Lafayette IN, US

International Classification:

G11C 7/02

US Classification:

365208000

Abstract:

A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

US Patent:

20090190426, Jul 30, 2009

Filed:

Jan 24, 2008

Appl. No.:

12/019132

Inventors:

Jae-Joon Kim - Austin TX, US
Niladri N. Mojumder - West Lafayette IN, US
Saibal Mukhopadhyay - Atlanta GA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/44

US Classification:

36521011, 365201

Abstract:

The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided.