Ryan C Kinter

US Patent:

6836833, Dec 28, 2004

Filed:

Oct 22, 2002

Appl. No.:

10/278537

Inventors:

Ryan C. Kinter - Sunnyvale CA
Scott M. McCoy - Palo Alto CA
Gideon D. Intrater - Sunnyvale CA

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 1200

US Classification:

711173, 711133

Abstract:

The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configurations of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.

US Patent:

6961819, Nov 1, 2005

Filed:

Apr 26, 2002

Appl. No.:

10/135004

Inventors:

Gideon D. Intrater - Sunnyvale CA, US
Anders M. Jagd - Mountain View CA, US
Ryan C. Kinter - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F012/00

US Classification:

711123, 711154

Abstract:

A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing.

US Patent:

7315937, Jan 1, 2008

Filed:

Oct 1, 2004

Appl. No.:

10/956490

Inventors:

Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Los Altos CA, US
Rivka Shenhav - Saratoga CA, US
Radhika Thekkath - Palo Alto CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 7/76

US Classification:

712300

Abstract:

A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instruction. The bit extraction instruction includes copying the size value number of bits from the accumulator beginning at the position value into a target register, setting any remaining bits of the target register to zero, and decrementing the position value by an amount based on the size value. The method may include loading bits from a bit stream into a register and moving the contents of the register into the accumulator to replenish the accumulator. The method may include determining, based on the position value, whether the accumulator needs to be replenished, and if not, branching to bypass replenishing functions.

US Patent:

7509456, Mar 24, 2009

Filed:

Dec 3, 2004

Appl. No.:

11/003120

Inventors:

Ryan C. Kinter - Sunnyvale CA, US
Scott M. McCoy - Palo Alto CA, US
Gideon D. Intrater - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 12/00

US Classification:

711118

Abstract:

The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.

US Patent:

7558939, Jul 7, 2009

Filed:

Mar 8, 2005

Appl. No.:

11/075041

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US
Ryan C. Kinter - Sammamish WA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711205, 711206, 711207

Abstract:

A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

US Patent:

7594089, Sep 22, 2009

Filed:

Sep 30, 2004

Appl. No.:

10/955231

Inventors:

Sanjay Vishin - Sunnyvale CA, US
Kevin D. Kissell - Le Bar sur Loup, FR
Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Los Altos CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711168, 711154, 711156, 711158, 711167

Abstract:

A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one memory location responsive to a memory access instruction relating to the particular one memory location, the interface including: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each the memory access instruction issued from an associated independent thread context; an arbiter, coupled to the request storage, for selecting a particular one of the memory access instructions to apply to the gating memory; and a controller, coupled to the request storage and to the arbiter, for: storing the plurality of memory access instructions in the request storage; initiating application of the particular one memory access instruction selected by the arbiter to the gating memory; receiving the particular one access method associated with the particular one memory access method from the gating memory; and initiating a communication of the particular access method to the thread context associated with the particular one access instruction.

US Patent:

7613904, Nov 3, 2009

Filed:

Feb 4, 2005

Appl. No.:

11/051997

Inventors:

Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Sammamish WA, US
Kevin D. Kissell - Le Bar sur Loup, FR
Thomas A. Petersen - San Francisco CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/50

US Classification:

712214, 718103

Abstract:

A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.

US Patent:

7627794, Dec 1, 2009

Filed:

May 25, 2006

Appl. No.:

11/442695

Inventors:

Ryan C. Kinter - Sammamish WA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G01R 31/28

US Classification:

714724

Abstract:

An electronic circuit includes multiple computational cores. A test access protocol machine with a core address register and a signal routing control circuit addresses a selected computational core as specified by the core address register and routes output test data from the selected computational core.