Russ W Herrell

US Patent:

6574710, Jun 3, 2003

Filed:

Jul 31, 2000

Appl. No.:

09/629128

Inventors:

Blaine D. Gaither - Ft Collins CO
Russ W Herrell - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711122, 711141, 711146

Abstract:

A lower level cache detects when a line of memory has been evicted from a higher level cache. The lower level cache stores the address of the evicted line. When the system bus is idle, the lower level cache initiates a transaction causing all higher level caches to invalidate the line. The lower level cache then places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed.

US Patent:

6868481, Mar 15, 2005

Filed:

Oct 31, 2000

Appl. No.:

09/704176

Inventors:

Blain D. Gaither - Ft Collins CO, US
Russ W Herrell - Ft Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F012/00

US Classification:

711119, 711141, 711144, 711145

Abstract:

A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

US Patent:

7373457, May 13, 2008

Filed:

Feb 1, 2005

Appl. No.:

11/049306

Inventors:

Blain D. Gaither - Ft Collins CO, US
Russ W Herrell - Ft Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711119, 711141, 711144, 711145

Abstract:

A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

US Patent:

7480755, Jan 20, 2009

Filed:

Dec 8, 2004

Appl. No.:

11/006964

Inventors:

Russ Herrell - Fort Collins CO, US
John A. Morrison - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/24

US Classification:

710269, 710260, 710268

Abstract:

Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

US Patent:

7600082, Oct 6, 2009

Filed:

Nov 30, 2004

Appl. No.:

11/000279

Inventors:

Russ Herrell - Fort Collins CO, US
John A. Morrison - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/14

US Classification:

711154, 711100, 711163, 711200, 711203

Abstract:

Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.

US Patent:

7606995, Oct 20, 2009

Filed:

Jul 23, 2004

Appl. No.:

10/898590

Inventors:

Russ Herrell - Fort Collins CO, US
John A. Morrison - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 15/00

US Classification:

712 13

Abstract:

Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

US Patent:

7650275, Jan 19, 2010

Filed:

Jan 20, 2005

Appl. No.:

11/039621

Inventors:

Russ Herrell - Fort Collins CO, US
John A. Morrison - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06G 7/48
G06F 9/44
G06F 13/10
G06F 13/12
G06F 9/455

US Classification:

703 25, 703 4, 703 21, 718 1

Abstract:

Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.

US Patent:

7694064, Apr 6, 2010

Filed:

Dec 29, 2004

Appl. No.:

11/024575

Inventors:

Mark Shaw - Garland TX, US
Russ William Herrell - Fort Collins CO, US
Stuart Allen Berke - Austin TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/00

US Classification:

710317, 710316, 712 11, 326 41, 709249

Abstract:

In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect the multiple cells with the global crossbar network. In an embodiment, the system further includes at least one cell-to-cell connector, to directly connect at least one pair of the multiple cells. In another embodiment, the system further includes one or more local crossbar networks, multiple cell-to-local-crossbar connectors, and local input/output backplanes connected to the one or more local crossbar networks.