Roy Espe

US Patent:

43575471, Nov 2, 1982

Filed:

Feb 23, 1981

Appl. No.:

6/237322

Inventors:

Roy H. Espe - Scottsdale AZ
W. Eric Main - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 3289

US Classification:

307272A

Abstract:

A toggle flip-flop of the type which is controlled by a clock signal capable of assuming high and low states includes a master circuit portion and a slave circuit portion. The master circuit portion includes a first output stage which is latched when the clock signal is high while the slave circuit portion has an output stage which is latched when the clock signal is low. A driving voltage signal is produced in the slave circuit portion for driving the second output stage. Means are provided for inverting the driving voltage signal and for using the inverted version to drive the first output stage.

US Patent:

55838910, Dec 10, 1996

Filed:

Oct 31, 1994

Appl. No.:

8/332171

Inventors:

Roy H. Espe - Scottsdale AZ
Richard Potyka - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 106
H04B 710

US Classification:

375346

Abstract:

A noise attenuation circuit (43) is provided for reducing noise in an RF stage of an AM radio receiver. A RF amplifier (44) amplifies an RF signal with amplitude modulated audio information from the signal path of an AM receiver. An AM detector (46) receives the amplified RF signal and removes the audio information. A high-pass filter (47) filters out a majority of the audio information. A noise pulse couples through the hi-pass filter (47) which is detected by a pulse detector (48) when above a predetermined threshold voltage. The pulse detector (48) enables an RF timer (49) for generating a pulse of a predetermined width. The RF timer enables a RF attenuator (51) for attenuating the RF signal in the signal path of the AM receiver. The RF attenuator (51) attenuates an average noise pulse to a level approximately equal to the magnitude of an unmodulated RF signal.

US Patent:

48900729, Dec 26, 1989

Filed:

Feb 3, 1988

Appl. No.:

7/151870

Inventors:

Roy H. Espe - Scottsdale AZ
Lawrence M. Ecklund - Whenton IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 710

US Classification:

331 11

Abstract:

A circuit for use in a phase locked loop (PLL) which is responsive to the PLL being out of lock for providing fast lock current to drive the VCO of the PLL in the direction to acquire lock. The circuit includes a pair of controlled current sources responsive to selective control signals for either sourcing or sinking fast lock current at the output of the circuit that are utilized to produce an error control voltage at the loop filter to drive the VCO accordingly while a reducing circuit is responsive to the control voltage reaching a predetermined value as the VCO is driven toward one end or the other of its range for clamping the control voltage while reducing the fast lock current to a reduced value thereby limiting excessive charge build-up on the loop filter capacitor of the PLL. Thus, the circuit permits the VCO to acquire fast lock up by providing fast lock current thereto while clamping the range of the VCO and reducing the fast lock current as the VCO approaches either end of its range. Upon acquiring lock up, the controlled current sources are disabled.