Ronald J Setera

US Patent:

42310890, Oct 28, 1980

Filed:

Dec 15, 1978

Appl. No.:

5/969956

Inventors:

Donald A. Lewine - Marlborough MA
Thomas M. Dundon - Marlborough MA
Ronald J. Setera - Leominster MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1116

US Classification:

364200

Abstract:

In a data processing system, a method and apparatus which enable an erroneous microinstruction word to be rewritten before it is executed. After the microinstruction word is written from memory into a control register, a parity network coupled to the control register determines whether a correct microinstruction is being executed. Upon a parity error being detected, the clock pulses to the data paths coupled to the control register are inhibited. The original microinstruction word is then fetched from secondary storage and rewritten into the microinstruction memory with the aid of a separate register providing the address to the microinstruction memory. Upon rewriting the microinstruction memory, the signal inhibiting the clock pulses is removed thereby allowing a new microinstruction to be executed. An additional feature includes apparatus for determining whether an error has previously occurred for the same microinstruction word, in which case a critical fault occurs and remedial maintenance is necessary.