Roberto Sung

US Patent:

6353568, Mar 5, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/752357

Inventors:

Roberto Sung - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365207, 365205, 327 57

Abstract:

A dual threshold voltage sense amplifier that is capable of separating the rise time threshold from the fall time threshold, creating a dual sensing threshold voltage. In one embodiment of the invention, the dual threshold voltage sense amplifier is capable of providing a lower threshold for the rise time and a higher threshold for the fall time, thereby reducing the fall time and improving the read speed in asynchronous static memory without substantially increasing the core cell dimension or the overall design size.

US Patent:

6347026, Feb 12, 2002

Filed:

May 26, 1999

Appl. No.:

09/320013

Inventors:

Roberto Sung - Cupertino CA
Jau-Wen Chen - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H02H 900

US Classification:

361 56, 361111

Abstract:

Fabricated using a complementary metal oxide semiconductor process including the use of salicides, an input and power protection circuit for use in an integrated circuit protects voltage and signal terminals from both overvoltage and ESD pulses. A diode connected is connected between a first terminal and an inter-transistor node, a field effect transistor is connected between the inter-transistor node and a second terminal, and a lateral bipolar transistor, with a base connected to the inter-transistor node, is connected between the first and the second terminals. When an ESD pulse appears on the first terminal, the voltage at the inter-transistor node increases until a snapback trigger voltage of the field effect transistor is reached whereupon current flows from the first terminal, through the emitter-base junction of the lateral bipolar transistor, through the inter-transistor node, through the field effect transistor, and to the second terminal. In response to the current flow through the inter-transistor node, the lateral bipolar transistor substantially increases the current flow from the first terminal, through the lateral bipolar transistor, and to the second terminal so that a majority of current will flow through this path. Similarly, when an ESD pulse appears on the second terminal, this creates current flow from the second terminal, through the collector-base junction of the lateral bipolar transistor, through the inter-transistor node, through the diode, and to the first terminal.