Robert M Sebesta

US Patent:

6351393, Feb 26, 2002

Filed:

Jul 2, 1999

Appl. No.:

09/346356

Inventors:

John S. Kresge - Binghamton NY
Robert D. Sebesta - Endicott NY
David B. Stone - Jericho VT
James R. Wilcox - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 114

US Classification:

361795, 361748, 361792, 361793, 174252, 174255, 174260, 174261, 174266, 257700, 257702, 257698, 257759, 257642

Abstract:

An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg. , circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

US Patent:

6373717, Apr 16, 2002

Filed:

Mar 31, 2000

Appl. No.:

09/540172

Inventors:

Donald S. Farquhar - Endicott NY
Elizabeth Foster - Friendsville PA
Robert M. Japp - Vestal NY
Gerald W. Jones - Apalachin NY
John S. Kresge - Binghamton NY
Robert D. Sebesta - Endicott NY
David B. Stone - Jericho VT
James R. Wilcox - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 118

US Classification:

361795, 361792, 361793, 361794, 361748, 174255, 174266, 174262, 257700, 257698, 438125

Abstract:

An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg. , circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

US Patent:

6429113, Aug 6, 2002

Filed:

Mar 3, 2000

Appl. No.:

09/518447

Inventors:

Robert Lee Lewis - Apalachin NY
Robert David Sebesta - Endicott NY
Daniel Martin Waits - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438612, 438106, 438125, 438613

Abstract:

A method of making a circuitized substrate for use in an electronic package wherein the substrate, e. g. , ceramic, includes more than one conductive layer, e. g. , copper, thereon separated by a suitable dielectric material, e. g. , polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e. g. using solder, to respective contact sites on a semiconductor chip to form part of the final package. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations; these locations, as mentioned, instead being directly connected to the chip.

US Patent:

6538213, Mar 25, 2003

Filed:

Feb 18, 2000

Appl. No.:

09/506951

Inventors:

Timothy F. Carden - Vestal NY
Todd W. Davies - Vestal NY
Ross W. Keesler - Endicott NY
Robert D. Sebesta - Endicott NY
David B. Stone - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01R 1204

US Classification:

174262, 174260

Abstract:

An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

US Patent:

6580491, Jun 17, 2003

Filed:

Dec 26, 2000

Appl. No.:

09/749044

Inventors:

Richard Ronald Hall - Endwell NY
Robert Lee Lewis - Apalachin NY
How Tzu Lin - Vestal NY
Peter Michael Nichols - Johnson City NY
Robert David Sebesta - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03B 2768

US Classification:

355 52, 355 53, 356399, 356401

Abstract:

Apparatus and method for compensating for distortion of the substrate of a printed circuit workpiece that involves performing two tasks. First, a mask that carries functional circuit features and alignment features is positioned rotatably so that the mask alignment features, when projected onto a table that holds the printed circuit workpiece, will be on a line extending parallel to one of two orthogonal axes of the table. Second, the spacing of alignment features on the printed circuit workpiece is determined and this determination is a measure of the distortion of the printed circuit workpiece substrate. A lens through which the mask image is projected is moved to adjust the magnification of the image in accordance with the measured distortion of the substrate of the printed circuit workpiece.

US Patent:

6580494, Jun 17, 2003

Filed:

Jul 16, 2002

Appl. No.:

10/198383

Inventors:

Richard Ronald Hall - Endwell NY
Robert Lee Lewis - Apalachin NY
How Tzu Lin - Vestal NY
Peter M. Nichols - Johnson City NY
Robert David Sebesta - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03B 2752

US Classification:

355 55

Abstract:

A photolithography imaging system and method that performs the tasks of mask alignment, panel recognition, establishing position offsets and adjusting mask rotation for accurate overlay imaging of the mask onto the panel, and correctly adjusting image magnification or reduction to properly size each stepped image to the panel distortion. This invention applies more directly to substrate panels whose dimensional stability is found difficult to control, repeatedly. More specifically, it applies to panels whose X axis distortion factor varies greatly from its Y axis distortion factor and the average adjustment of the image magnification or reduction does not satisfy tight registration requirements. What is new is that the calculation of the magnification or reduction adjustment is based on the mask image dimensions.

US Patent:

6618940, Sep 16, 2003

Filed:

Jul 19, 2001

Appl. No.:

09/909211

Inventors:

Kenneth J. Lubert - Endicott NY
Curtis L. Miller - Vestal NY
Thomas R. Miller - Endwell NY
Robert D. Sebesta - Endicott NY
James W. Wilson - Vestal NY
Michael Wozniak - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 310

US Classification:

29846, 29847, 29852, 174265, 174266, 216 19, 216 38, 216 41, 427 97, 427123, 430314, 430318

Abstract:

A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

US Patent:

6815709, Nov 9, 2004

Filed:

May 23, 2001

Appl. No.:

09/863978

Inventors:

Ronald Clothier - Vestal NY
Jeffrey Alan Knight - Endwell NY
Robert David Sebesta - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 3524

US Classification:

257 40, 257202, 257203, 257210, 257211

Abstract:

Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Author:

Robert W. Sebesta

ISBN #:

0139279555

Author:

Robert W. Sebesta

ISBN #:

0201385961

Author:

Robert W. Sebesta

ISBN #:

0201704846

Author:

Robert W. Sebesta

ISBN #:

0201752956

Author:

Robert W. Sebesta

ISBN #:

0075541203

Author:

Robert W. Sebesta

ISBN #:

0321149459

Author:

Robert W. Sebesta

ISBN #:

0321193628

Author:

Robert W. Sebesta

ISBN #:

0321303326