Robert E Rutter

US Patent:

47663634, Aug 23, 1988

Filed:

May 29, 1987

Appl. No.:

7/055294

Inventors:

Robert E. Rutter - Tempe AZ
Robert M. Jensen - Albuquerque NM

Assignee:

Devore Aviation Corporation - Albuquerque NM

International Classification:

G05F 140

US Classification:

323243

Abstract:

Power from an AC source is applied to a load under control of a power switching triac in response to signals from a feedback loop isolated from line voltage transients by means of a pair of opto-coupling devices respectively connecting the feedback loop to a load voltage sensor and the control electrode of the triac.

US Patent:

53230590, Jun 21, 1994

Filed:

Oct 26, 1992

Appl. No.:

7/966822

Inventors:

Robert E. Rutter - Tempe AZ
Frank S. d'Aragona - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348
H01L 2352
H01L 2940
H01L 2974

US Classification:

257768

Abstract:

Briefly stated, the present invention provides a vertical current flow semiconductor device (17). The vertical current flow semiconductor device (17) includes a semiconductor substrate (12) having an intermediate conductor layer (16) on a surface of the substrate (12). An active layer (11) that is used for forming active elements (20, 21, 22, 23) of the vertical current flow semiconductor device (17) is on the intermediate conductor layer (16). The intermediate conductor layer (16) forms an ohmic contact with the active layer (11).

US Patent:

51418894, Aug 25, 1992

Filed:

Jun 17, 1991

Appl. No.:

7/715864

Inventors:

Lewis E. Terry - Phoenix AZ
Stephen P. Robb - Tempe AZ
Robert E. Rutter - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265
H01L 21328

US Classification:

437 31

Abstract:

An insulated gate bipolar device is formed on a multiple conductivity substrate. The multiple conductivity substrate comprises interspersed regions of N+ and P+ semiconductor material. In a preferred embodiment, the N+ and P+ regions are arranged in a checkerboard, mosaic pattern on a bottom side of the substrate. The P+ region serves to conductivity modulate an N epitaxial layer in which the IGBT structure is formed while the N+ regions improve low current conductivity, reduce minority carrier recombination time, and make an integral drain source diode accessible from the drain and source electrodes.

US Patent:

52571556, Oct 26, 1993

Filed:

Aug 23, 1991

Appl. No.:

7/749020

Inventors:

Stephen P. Robb - Tempe AZ
Robert E. Rutter - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 710

US Classification:

361 18

Abstract:

A protection circuit for providing short-circuit protection for a field effect transistor has been provided. The protection circuit senses when the voltage appearing at the gate and drain electrodes of the field effect transistor are both at a logic high voltage level, and responds to turn off the field effect transistor thereby preventing damage to the field effect transistor.

US Patent:

51837692, Feb 2, 1993

Filed:

May 6, 1991

Appl. No.:

7/696405

Inventors:

Robert E. Rutter - Tempe AZ
Frank S. d'Aragona - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2970

US Classification:

437 31

Abstract:

An intermediate contact layer (16) is created within a vertical current flow semiconductor device such as an enhanced insulated gate bipolar transistor (EIGBT) (17). An active wafer (11) that is used for forming active elements of the device is wafer bonded to a conductor (16) that is on a surface of a substrate wafer (12). The wafer bonding not only forms the intermediate contact layer (16) but also diffuses a series of P (18) and N (19) regions into the active wafer (11) thereby forming ohmic contacts between the P (18) and N (19) regions and the intermediate contact layer (16). The substrate wafer (12) provides support for the active wafer (11) during subsequent wafer processing operations.

US Patent:

59279931, Jul 27, 1999

Filed:

Feb 3, 1992

Appl. No.:

7/829660

Inventors:

Israel A. Lesk - Phoenix AZ
Robert B. Davies - Tempe AZ
Robert E. Rutter - Tempe AZ
Lowell E. Clark - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21301

US Classification:

438455

Abstract:

A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.