Robert A Neidorff

US Patent:

6646513, Nov 11, 2003

Filed:

Aug 28, 2002

Appl. No.:

10/229486

Inventors:

Robert Alan Neidorff - Bedford NH

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 302

US Classification:

331143, 331111

Abstract:

An oscillator circuit ( ) disclosed herein includes an improved capacitor discharge circuit. The oscillator includes at least one capacitor coupled to a charging circuit portion ( ) and a discharging circuit portion ( ) through a switching network ( and ). In the alternative, an oscillator including more than one capacitor includes respective charging and discharging circuit portions connected to respective switching networks. Each charging circuit portion ( ) provides sufficient charge to charge the coupled capacitor ( ) to a high threshold voltage (V ). Each discharging circuit portion ( ) discharges each coupled capacitor ( ) to a low threshold voltage (V ). The switching network alternately connects each coupled capacitor ( ) to the charging circuit portion ( ) and the discharging circuit portion ( ) to thereby alternately charge and discharge for each coupled capacitor ( ) alternately. A set/reset flip-flop ( ) connected to the switching network ( and ) enables and disenables the charging cycle and the discharge cycle of the oscillator.

US Patent:

6995599, Feb 7, 2006

Filed:

Aug 26, 2003

Appl. No.:

10/649226

Inventors:

Robert Neidorff - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 17/62

US Classification:

327408

Abstract:

Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator. The power selection circuitry may be employed in a redundant power supply to block the cross-conduction of current between the multiple input voltage sources, to reduce current spikes during power selection switching, and to satisfy NTC trip voltage requirements of the switching elements connecting the input voltage sources to the load.

US Patent:

7061291, Jun 13, 2006

Filed:

Dec 22, 2003

Appl. No.:

10/743171

Inventors:

Karl H. Jacobs - Pleasant Valley CT, US
Robert Neidorff - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 5/12

US Classification:

327170, 327 95

Abstract:

Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +V, the level shifter provides a voltage to the input resistor that ramps up from −Vto 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to −V, thereby providing a negative output supply voltage −Vwith a slew rate that linearly tracks the slew rate of the master positive output supply.

US Patent:

7088171, Aug 8, 2006

Filed:

Jun 13, 2003

Appl. No.:

10/461986

Inventors:

Robert Alan Neidorff - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 3/02

US Classification:

327536, 363 59

Abstract:

An improved charge pump circuit that is capable of producing a constant output current. The charge pump circuit includes a controllable current source, at least one switching element coupled between the controllable current source and an output node, and a load capacitor coupled between the output node and ground potential. The switching element switches in response to an input signal to allow current pulses to flow from the controllable current source through the output node. The load capacitor operates as an integrator to convert the output current pulses into a voltage level. The controllable current source provides increased current levels as the output voltage level of the charge pump increases, thereby enhancing the overall efficiency of the charge pump circuit.

US Patent:

7504895, Mar 17, 2009

Filed:

Apr 10, 2007

Appl. No.:

11/786059

Inventors:

Robert Alan Neidorff - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 7/24

US Classification:

331 55, 331 46

Abstract:

An oscillator for synchronizing and controlling a multi-phase, interleaved power supply system that has a plurality of power sources. The oscillator includes a first oscillator, having a pulse generator and a timing capacitor, and a second oscillator, having a pulse generator and timing capacitor, that are electrically coupled to one or more first power supplies and one or more second power supplies, respectively. The pulse generator of the first oscillator is electrically coupled to the second timing capacitor and the pulse generator of the second oscillator is electrically coupled to the first timing capacitor. Each of the pulse generators is structured and arranged to provide a synchronizing pulse to the other oscillator's timing capacitor when the voltage on its own timing capacitor is midway between a pre-determined maximum voltage threshold and a pre-determined minimum voltage threshold.

US Patent:

7536566, May 19, 2009

Filed:

Sep 26, 2005

Appl. No.:

11/234899

Inventors:

Steven M. Hemmah - Goffstown NH, US
Robert A. Neidorff - Bedford NH, US
Jonathan M. Bearfield - Raymond NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/00

US Classification:

713300, 713320, 713330, 713340

Abstract:

Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.

US Patent:

7550980, Jun 23, 2009

Filed:

Aug 1, 2007

Appl. No.:

11/888467

Inventors:

Jean Picard - Hooksett NH, US
Lin Wang - Merrimack NH, US
Wilburn M. Miller - Wilton NH, US
Robert A. Neidorff - Bedford NH, US
Guillermo J. Serrano - Coto Laurel PR, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 27/08
H02H 3/20

US Classification:

324705, 324691, 361 912

Abstract:

Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable is within an acceptable resistance range. If the load is within the acceptable resistance range, a voltage source is coupled to the load. In one embodiment one recharge interval is employed during which a capacitor is charged based, at least in part, on the voltage drop across the load and one discharge interval is employed during which a capacitor is discharged based, at least in part, on the voltage drop across the load. In a second embodiment, first and second recharge and discharge intervals are employed and prior to initiation of the recharge and discharge intervals, settling time periods are provided.

US Patent:

7567134, Jul 28, 2009

Filed:

May 1, 2007

Appl. No.:

11/799181

Inventors:

Isaac Cohen - Dix Hills NY, US
Robert A. Neidorff - Bedford NH, US
Richard L. Valley - Nashua NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03B 27/00

US Classification:

331 45, 331 57, 331 1 A, 331 2

Abstract:

A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.